公开(公告)号：US5003204A

公开(公告)日：1991-03-26

申请号：US452883

申请日：1989-12-19

Applicant: David E. Cushing ,  John A. DeFalco

Inventor： David E. Cushing ,  John A. DeFalco

IPC: H03K3/037

CPC classification number: H03K3/037

Abstract: A synchronous latch device macrocell which includes an input gate section and a scannable latch section. Both sections are directly connected together to provide a non-inverting path for input data signals thereby eliminating the need for internal inverting buffer circuits. The non-inverting output of the latch section connects to an output pin and provides a signal representation of the state of the latch device. The output pin is externally connected through a conductor wire to either one of a pair of complementary data input pins of the input gate section. The connection made is selected as a function of which data input pin connection provides the faster loading of the latch device as viewed from the source of the signal applied to the load control pin of the input gate section.

公开(公告)号：US4445083A

公开(公告)日：1984-04-24

申请号：US296382

申请日：1981-08-26

Applicant: John A. DeFalco

Inventor： John A. DeFalco

IPC: G05F1/46 ,  G05F1/56 ,  H01L27/02

CPC classification number: G05F1/466

Abstract: Apparatus adjusts the low supply voltage applied to the bipolar gate array circuits of a semiconductor chip to provide uniform propagation delay in the signals operated on by the array circuits notwithstanding variations in manufacturing tolerances and temperature variations. The apparatus includes a voltage regulator circuit and a first resistor located off the chip connected between its output and adjustment terminals and a second resistor located on the chip connected to the adjustment terminal of the regulator circuit. The voltage regulator circuit in response to changes in the resistance of the second resistor adjusts the low supply voltage at its output terminal so as to provide uniform signal delays through the array circuits.

Abstract translation: 设备调节施加到半导体芯片的双极性栅极阵列电路的低电源电压，以在由阵列电路操作的信号中提供均匀的传播延迟，尽管制造公差和温度变化的变化。 该装置包括电压调节器电路和位于其输出和调节端子之间的芯片上的第一电阻器和位于连接到调节器电路的调整端子的芯片上的第二电阻器。 电压调节器电路响应于第二电阻器的电阻的变化调节其输出端子处的低电源电压，以便通过阵列电路提供均匀的信号延迟。

公开(公告)号：US06803821B1

公开(公告)日：2004-10-12

申请号：US10406334

申请日：2003-04-03

Applicant: John A. DeFalco ,  Mikhail S. Shirokov

Inventor： John A. DeFalco ,  Mikhail S. Shirokov

IPC: H03F304

CPC classification number: H03F3/72

Abstract: A switchable amplifier circuit having a current mirror. The mirror includes: a first current source for producing a reference current; an output transistor having an input electrode and an output electrode; and a current gain device connected between an output of the first current source and the input electrode of the output transistor. A bias current is produced through the output electrode of the output transistor, such bias current being a function of the reference current produced by the first current source. A second current source has an output coupled to an input of the current gain device. The second current source provides a current which is a fraction of the reference current. A switching transistor has an output electrode coupled to: (1) an input of the current gain device; and, (2) an output of the second current source. The switching transistor: (1) sinks the current from the second current source in response to an input signal fed to such switching transistor inhibiting current from the second current source to pass to the current gain device and thereby remove the bias current for the output transistor driving the output transistor to a non-conducting condition; or (2) enables the current from the second current source to pass to the current gain device in response to the input signal fed to such switching transistor driving the output transistor to a conducting condition.

Abstract translation: 一种具有电流镜的可切换放大器电路。 镜子包括：用于产生参考电流的第一电流源; 具有输入电极和输出电极的输出晶体管; 以及连接在第一电流源的输出端和输出晶体管的输入电极之间的电流增益器件。 通过输出晶体管的输出电极产生偏置电流，这样的偏置电流是由第一电流源产生的参考电流的函数。 第二电流源具有耦合到当前增益器件的输入的输出。 第二个电流源提供的电流是参考电流的一部分。 开关晶体管具有耦合到：（1）电流增益器件的输入的输出电极; 和（2）第二电流源的输出。 开关晶体管：（1）响应于馈送到这种开关晶体管的输入信号，从第二电流源吸收电流，阻止来自第二电流源的电流传递到电流增益器件，从而去除输出晶体管的偏置电流 将输出晶体管驱动到非导通状态; 或者（2）使得来自第二电流源的电流响应于馈送到驱动输出晶体管的导通条件的这种开关晶体管的输入信号而传递到电流增益器件。

公开(公告)号：US06424224B1

公开(公告)日：2002-07-23

申请号：US09897749

申请日：2001-07-02

Applicant: Michael McPartlin ,  John A. DeFalco

Inventor： Michael McPartlin ,  John A. DeFalco

IPC: H03F304

CPC classification number: H03F1/302 ,  H01L25/18 ,  H01L2924/0002 ,  H01L2924/3011 ,  H03F1/301 ,  H03F3/191 ,  H03F3/193 ,  H03F3/211 ,  H03F3/345 ,  H01L2924/00

Abstract: An amplifier having a two different single crystal semiconductor substrates. A first one of the substrates has formed thereon at least one input signal amplifying device, such device comprising a bipolar transistor. A second one of the substrates is a material different from the material of the first substrate. A current mirror is included. The current mirror includes a plurality of electrically interconnected active devices, one portion of the devices being bipolar devices formed on the first substrate and another portion of the active devices comprising an insulated gate field effect transistor formed on the second substrate. The first single crystal substrate is III-V material and the second single crystal substrate is silicon. The bipolar devices are HBTs. The insulated gate field effect transistor is a MOS device. This configuration minimizes the effect of temperature, voltage and process variations on critical transistor operating currents.

Abstract translation: 具有两个不同单晶半导体衬底的放大器。 衬底中的第一个在其上形成有至少一个输入信号放大器件，该器件包括双极晶体管。 基板中的第二个是与第一基板的材料不同的材料。 包括当前镜。 电流镜包括多个电互连有源器件，器件的一部分是形成在第一衬底上的双极器件，另一部分有源器件包括形成在第二衬底上的绝缘栅场效应晶体管。 第一单晶衬底是III-V材料，第二单晶衬底是硅。 双极器件是HBT。 绝缘栅场效应晶体管是MOS器件。 该配置最大限度地减少了温度，电压和工艺变化对关键晶体管工作电流的影响。

公开(公告)号：US06600301B1

公开(公告)日：2003-07-29

申请号：US10135719

申请日：2002-04-30

Applicant: John A. DeFalco

Inventor： John A. DeFalco

IPC: G05F304

CPC classification number: G05F1/468

Abstract: An integrated circuit biasing network for producing .a.predetermined level of bias current. The bias network includes a field-effect transistor having a gate, a source and a drain. The transistor produces a level of bias current corresponding to a predetermined input gate-source voltage applied to the field effect transistor. A control circuit is provided. The control circuit is connected to the field effect transistor and provides a current through a control current path to produce the field effect transistor input voltage. A compensation circuit is connected to the control circuit. The compensation circuit includes a compensation transistor of the same type as the field effect transistor. The compensation circuit operates the compensation transistor to divert current from said control path whereby process variations cause the compensation transistor to draw a current of a magnitude to provide an input voltage to the field effect transistor to enable such field effect transistor to produce said predetermined level of bias current. A transistor switch is provided having a first and second electrode. Conductivity between such first and second electrodes is controlled by an “on”/“off” control signal fed to a control electrode of such transistor switch. One of such first and second electrodes is coupled to the gate of the field effect transistor and the other one of the first and second electrodes is coupled to a predetermined reference potential. The transistor switch is placed in a conductive condition by the “on”/“off ” control signal to couple the gate of the field effect transistor to such reference potential during an “off” condition of the control signal. Such coupling to the reference potential turns the field effect transistor to a non-conducting state during such “off” condition. The transistor switch is placed in a non-conductive condition to de-couple the gate of the field effect transistor from such reference potential during an “on” condition of the control signal to enable the field effect transistor to amplify a signal fed to the gate thereof during such “on” condition. The reference potential is coupled to the control circuit. The field effect transistor, the compensation transistor and the transistor switch are depletion mode field effect transistors. The compensation circuit is coupled between a second reference potential and the first-mentioned reference potential.