公开(公告)号：US20130215911A1

公开(公告)日：2013-08-22

申请号：US13849224

申请日：2013-03-22

Applicant: David P. Chengson ,  Jaya Bandyopadhyay

Inventor： David P. Chengson ,  Jaya Bandyopadhyay

IPC: H04J3/06

CPC classification number: H04J3/06 ,  G06F13/4022 ,  H04J3/0697 ,  H04L7/0008

Abstract: A multi-interface bus allows for different bus standards to be implemented over the same set of physical bus lines. More particularly, in one implementation, the system includes a first circuit board, a second circuit board, and a bus connecting the first and second circuit boards. The second circuit board is configured to communicate with the first circuit board using either a synchronous or an asynchronous bus protocol determined based on a bus protocol used by the first circuit board.

Abstract translation: 多接口总线允许在同一组物理总线上实现不同的总线标准。 更具体地，在一个实施方式中，该系统包括第一电路板，第二电路板和连接第一和第二电路板的总线。 第二电路板被配置为使用基于由第一电路板使用的总线协议确定的同步或异步总线协议与第一电路板通信。

公开(公告)号：US5867419A

公开(公告)日：1999-02-02

申请号：US903042

申请日：1997-07-29

Applicant: David P. Chengson ,  William L. Schmidt ,  Unmesh Agarwala ,  Alan D. Foster ,  Edward C. Priest ,  John C. Manton ,  Ali Mira

Inventor： David P. Chengson ,  William L. Schmidt ,  Unmesh Agarwala ,  Alan D. Foster ,  Edward C. Priest ,  John C. Manton ,  Ali Mira

IPC: G11C5/00 ,  H01L25/18 ,  H03H11/00

CPC classification number: H01L25/18 ,  H01L2924/0002 ,  H01L2924/3011

Abstract: A processor-inclusive memory module (PIMM) is disclosed. In one embodiment of the present invention, the PIMM includes a printed circuit board having first and second opposing surfaces. The printed circuit board also has an address line formed therein. A first SRAM is mounted on the first surface of the printed circuit board. The present PIMM is further comprised of a second SRAM mounted on the second surface of the printed circuit board. The second SRAM is mounted on the second surface of the printed circuit board directly opposite the first SRAM mounted on the first surface of the printed circuit board. The first and second SRAMs are coupled to the address line by respective cache buses. A processor is also mounted on the first surface of the printed circuit board, and is coupled to the address line. In one embodiment of the invention, a heat sink is thermally coupled to the processor. The processor has a plurality of contact pads disposed thereon. Electrical connectors extend from the second surface of the printed circuit board. The electrical connectors are electrically coupled to respective contact pads of the processor. In the present PIMM, the electrical connectors are adapted to be removably attached to a mother board. In so doing, the present PIMM is removably attachable to a mother board.

Abstract translation: 公开了一种包含处理器的存储器模块（PIMM）。 在本发明的一个实施例中，PIMM包括具有第一和第二相对表面的印刷电路板。 印刷电路板还具有形成在其中的地址线。 第一SRAM安装在印刷电路板的第一表面上。 本PIMM还包括安装在印刷电路板的第二表面上的第二SRAM。 第二SRAM安装在印刷电路板的与安装在印刷电路板的第一表面上的第一SRAM直接相对的第二表面上。 第一和第二SRAM通过相应的高速缓存总线耦合到地址线。 处理器也安装在印刷电路板的第一表面上，并且耦合到地址线。 在本发明的一个实施例中，散热器热耦合到处理器。 处理器具有设置在其上的多个接触垫。 电连接器从印刷电路板的第二表面延伸。 电连接器电耦合到处理器的相应接触垫。 在目前的PIMM中，电连接器适于可拆卸地连接到母板。 这样做，现在的PIMM可拆卸地连接到母板上。

公开(公告)号：US5790612A

公开(公告)日：1998-08-04

申请号：US609068

申请日：1996-02-29

Applicant: David P. Chengson ,  Hansel A. Collins ,  Edward C. Priest ,  Scott W. Alvarez

Inventor： David P. Chengson ,  Hansel A. Collins ,  Edward C. Priest ,  Scott W. Alvarez

IPC: H03K5/13 ,  H03L7/081 ,  H03D3/24

CPC classification number: H03K5/131 ,  H03K5/133 ,  H03L7/0814

Abstract: The present invention incorporates a variable delay circuit to add delay to a clock signal. In a preferred embodiment of the present invention, the delay is determined and fixed by a circuit employing the concept of a lock-and-leave circuit. This has the effect of fine tuning the delay determined by the lock-and-leave circuit. Mode bits allow a user to control the rate at which fine tuning occurs. Three update rates are provided in a preferred embodiment of the present invention. They are slow, medium, and fast.

Abstract translation: 本发明包括一个可变延迟电路，以增加时钟信号的延迟。 在本发明的一个优选实施例中，通过使用锁定和离开电路的概念的电路来确定和固定延迟。 这具有微调由锁定和离开电路确定的延迟的效果。 模式位允许用户控制微调发生的速率。 在本发明的优选实施例中提供三个更新速率。 他们是缓慢，中等和快。

公开(公告)号：US20110267073A1

公开(公告)日：2011-11-03

申请号：US12769749

申请日：2010-04-29

Applicant: David P. CHENGSON ,  Granthana Rangaswamy

Inventor： David P. CHENGSON ,  Granthana Rangaswamy

IPC: G01R27/28

CPC classification number: G01R31/3171 ,  H04B3/487 ,  H04L1/24

Abstract: A system for testing link performance margin in a network device includes one or more daughter cards having a driver to transmit a signal and a receiver to receive the signal, and a midplane including a channel to transmit the signal from the driver to the receiver. The system includes multiple connector assemblies to connect the one or more daughter cards to the midplane, where each of the multiple connector assemblies includes a different known crosstalk margin value. A bit error rate tester is connected to a link between the driver and the receiver, and the multiple connector assemblies are interchangeably included in the link to approximate different signal-to-noise ratio margins for the tested link.

Abstract translation: 用于测试网络设备中的链路性能裕度的系统包括具有发送信号的驱动器和接收信号的接收器的一个或多个子卡，以及包括用于将信号从驱动器发送到接收器的信道的中间平面。 该系统包括用于将一个或多个子卡连接到中平面的多个连接器组件，其中多个连接器组件中的每一个包括不同的已知串扰余量值。 一个误码率测试仪被连接到驱动器和接收器之间的链路，并且多个连接器组件可互换地包括在链路中以近似不同的测试链路的信噪比裕量。

公开(公告)号：US5999437A

公开(公告)日：1999-12-07

申请号：US789557

申请日：1997-01-27

Applicant: David P. Chengson ,  William L. Schmidt ,  Unmesh Agarwala ,  Alan D. Foster ,  Edward C. Priest ,  John C. Manton ,  Ali Mira

Inventor： David P. Chengson ,  William L. Schmidt ,  Unmesh Agarwala ,  Alan D. Foster ,  Edward C. Priest ,  John C. Manton ,  Ali Mira

IPC: G06F15/78 ,  G11C5/00 ,  H01L25/18 ,  H05K7/14 ,  H05K1/14

CPC classification number: H05K7/1422 ,  G06F15/7864 ,  H01L25/18 ,  H01L2924/0002 ,  H01L2924/3011

Abstract: A processor-inclusive memory module (PIMM) is disclosed. In one embodiment of the present invention, the PIMM includes a printed circuit board having first and second opposing surfaces. The printed circuit board also has an address line formed therein. A first SRAM is mounted on the first surface of the printed circuit board. The present PIMM is further comprised of a second SRAM mounted on the second surface of the printed circuit board. The second SRAM is mounted on the second surface of the printed circuit board directly opposite the first SRAM mounted on the first surface of the printed circuit board. The first and second SRAMs are coupled to the address line by respective cache buses. A processor is also mounted on the first surface of the printed circuit board, and is coupled to the address line. In one embodiment of the invention, a heat sink is thermally coupled to the processor. The processor has a plurality of contact pads disposed thereon. Electrical connectors extend from the second surface of the printed circuit board. The electrical connectors are electrically coupled to respective contact pads of the processor. In the present PIMM, the electrical connectors are adapted to be removably attached to a mother board. In so doing, the present PIMM is removably attachable to a mother board.

公开(公告)号：US08508248B1

公开(公告)日：2013-08-13

申请号：US13024408

申请日：2011-02-10

Applicant: David P. Chengson

Inventor： David P. Chengson

IPC: G01R31/309

CPC classification number: G01R31/2812 ,  G01R31/11

Abstract: A device provides a time domain reflectometry (TDR) or a vector network analyzer (VNA) test signal to a via test area provided on a printed circuit board (PCB), where the via test area includes vias and via stubs formed in the vias. The device also receives a reflected signal from each via in the via test area of the PCB, and compares the reflected signal from each via to a minimum impedance threshold. The device further provides, for display, an indication of passing for the PCB, when the reflected signals from the vias are greater than the minimum impedance threshold.

Abstract translation: 设备向印刷电路板（PCB）上提供的通孔测试区域提供时域反射计（TDR）或矢量网络分析仪（VNA）测试信号，其中通孔测试区域包括形成在通孔中的通孔和通孔。 该器件还从PCB的通孔测试区域中的每个通孔接收反射信号，并将每个通孔的反射信号与最小阻抗阈值进行比较。 当来自过孔的反射信号大于最小阻抗阈值时，该装置还提供用于显示PCB通过的指示。

公开(公告)号：US08164392B2

公开(公告)日：2012-04-24

申请号：US12767194

申请日：2010-04-26

Applicant: David P. Chengson ,  Victor Do

Inventor： David P. Chengson ,  Victor Do

IPC: H03B1/00 ,  H03K17/28

CPC classification number: G06F1/04

Abstract: An isolation switch is used to isolate the output of an oscillator, during startup of the oscillator, from the circuitry that uses the periodic signal generated by the oscillator. In one implementation, a device may include an oscillator to generate a periodic signal and a switch connected to receive an output of the oscillator. The switch may include a control input that controls whether the switch is in an open or closed state. Switch control circuit may control the switch so that the switch is in an open state during startup of the oscillator and the switch is in a closed state thereafter.

Abstract translation: 隔离开关用于在振荡器启动期间将振荡器的输出与使用由振荡器产生的周期信号的电路隔离开来。 在一个实现中，设备可以包括用于产生周期性信号的振荡器和连接以接收振荡器的输出的开关。 开关可以包括控制输入，该控制输入控制开关是处于打开还是关闭状态。 开关控制电路可以控制开关，使得开关在振荡器启动期间处于打开状态，此后开关处于闭合状态。

公开(公告)号：US5036528A

公开(公告)日：1991-07-30

申请号：US471915

申请日：1990-01-29

Applicant: Duc N. Le ,  Lordson L. Yue ,  Cirillo L. Costantino ,  David P. Chengson ,  Duc N. Le ,  Lordson L. Yue ,  Aurangzeb K. Khan

Inventor： Duc N. Le ,  Lordson L. Yue ,  Cirillo L. Costantino ,  David P. Chengson ,  Duc N. Le ,  Lordson L. Yue ,  Aurangzeb K. Khan

IPC: G06F1/12 ,  G06F1/10 ,  H03K5/00

CPC classification number: G06F1/10

Abstract: The present invention is directed to a self-calibrating clock synchronization system that receives a periodic, digital clock signal as a reference and generates therefrom a system clock signal that dynamically tracks and is synchronized to the reference clock. The invention utilizes state machine controlled selection circuitry that comprises a plurality of predetermined delays tapped to produce a number of phase-related clock signals, and multiplexing circuitry, for selecting one of the plurality of clock signals as the system clock. A comparator compares the selected clock signal and the reference clock to determine which leads or lags the other. In response to the comparison, selection, from the plurality of clock signals, of a system clock that most clearly matches the reference signal is made.

公开(公告)号：US08452908B2

公开(公告)日：2013-05-28

申请号：US12648373

申请日：2009-12-29

Applicant: David P. Chengson ,  Chang-Hong Wu

Inventor： David P. Chengson ,  Chang-Hong Wu

IPC: G06F13/14 ,  G06F3/00 ,  G06F5/00 ,  G06F1/04 ,  G06F1/12 ,  G06F5/06

CPC classification number: G06F13/1689 ,  H04L25/03866 ,  H04L25/06

Abstract: A device applies synchronous clocking across a first component and a second component of the device, and designates a particular serial link, from a group of serial links, as a master serial link. The device also designates the remaining serial links as slave serial links, provides, via the master serial link, an encoded data stream, and provides, via the slave serial links, un-encoded and scrambled data streams.

Abstract translation: 一个设备跨设备的第一个组件和第二个组件应用同步时钟，并从一组串行链路指定一个特定的串行链路作为主串行链路。 该设备还将剩余的串行链路指定为从串行链路，通过主串行链路提供编码数据流，并通过从串行链路提供未编码和加扰的数据流。

公开(公告)号：US20110260769A1

公开(公告)日：2011-10-27

申请号：US12767194

申请日：2010-04-26

Applicant: David P. CHENGSON ,  Victor DO

Inventor： David P. CHENGSON ,  Victor DO

IPC: G06F1/04

CPC classification number: G06F1/04

Abstract: An isolation switch is used to isolate the output of an oscillator, during startup of the oscillator, from the circuitry that uses the periodic signal generated by the oscillator. In one implementation, a device may include an oscillator to generate a periodic signal and a switch connected to receive an output of the oscillator. The switch may include a control input that controls whether the switch is in an open or closed state. Switch control circuit may control the switch so that the switch is in an open state during startup of the oscillator and the switch is in a closed state thereafter.

Abstract translation: 隔离开关用于在振荡器启动期间将振荡器的输出与使用由振荡器产生的周期信号的电路隔离开来。 在一个实现中，设备可以包括用于产生周期性信号的振荡器和连接以接收振荡器的输出的开关。 开关可以包括控制输入，该控制输入控制开关是处于打开还是关闭状态。 开关控制电路可以控制开关，使得开关在振荡器启动期间处于打开状态，此后开关处于闭合状态。