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公开(公告)号：US07102365B1
公开(公告)日：2006-09-05
申请号：US11097593
申请日：2005-04-01
CPC分类号： G01R19/0023 , G01R1/203
摘要： Apparatus for sensing a current across a known resistor including a switched capacitor network and an amplifier having an input coupled to an output of the switched capacitor network. The switched capacitor network is configured to sample first and second reference potentials indicating the current. The amplifier is configured to produce first and second amplified potentials at an output of the amplifier based on the first and second reference potentials.
摘要翻译： 用于感测跨过已知电阻器的电流的装置，包括开关电容器网络和具有耦合到开关电容器网络的输出的输入的放大器。 开关电容器网络被配置为对指示电流的第一和第二参考电位进行采样。 放大器被配置为基于第一和第二参考电位在放大器的输出处产生第一和第二放大电位。
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公开(公告)号：US07282929B2
公开(公告)日：2007-10-16
申请号：US11493686
申请日：2006-07-25
IPC分类号： G01R27/08
CPC分类号： G01R19/0023 , G01R1/203
摘要： Apparatus for sensing a current across a known resistor comprising a switched capacitor network and an amplifier having an input coupled to an output of the switched capacitor network. The switched capacitor network is configured to sample first and second reference potentials indicating the current. The amplifier is configured to produce first and second amplified potentials at an output of the amplifier based on the first and second reference potentials.
摘要翻译： 用于感测跨过已知电阻器的电流的装置，包括开关电容器网络和具有耦合到开关电容器网络的输出的输入端的放大器。 开关电容器网络被配置为对指示电流的第一和第二参考电位进行采样。 放大器被配置为基于第一和第二参考电位在放大器的输出处产生第一和第二放大电位。
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公开(公告)号：US07015852B1
公开(公告)日：2006-03-21
申请号：US11001209
申请日：2004-11-30
IPC分类号： H03M1/12
CPC分类号： H03M1/403
摘要： A method and apparatus are provided for reducing the size and power of cyclic analog-to-digital converter (ADC) conversion circuits. During each cycle, the ADC conversion circuit generates a plurality of bits. The improved ADC includes a scaling/reference circuit having a single operational amplifier which operates in a reference generation mode and an analog multiplexing mode during generation of the first bit and operates in the analog multiplexing mode during generation of the subsequent bits.
摘要翻译： 提供了一种用于减小循环模数转换器（ADC）转换电路的尺寸和功率的方法和装置。 在每个周期期间，ADC转换电路产生多个位。 改进的ADC包括缩放/参考电路，该缩放/参考电路具有在产生第一位期间以参考生成模式和模拟复用模式操作的单个运算放大器，并且在后续位的生成期间以模拟复用模式操作。
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公开(公告)号：US07289052B1
公开(公告)日：2007-10-30
申请号：US11411352
申请日：2006-04-25
IPC分类号： H03M1/12
CPC分类号： H03M1/1225 , H03M1/0695 , H03M1/403
摘要： A system and method for converting an analog signal to a digital signal is provided including a first circuit (22) having a signal range and an input for receiving a first signal, and a second circuit (24) having an input receiving the analog signal and a first output coupled to the input of the first circuit. The first circuit (22) includes an amplifier (28). The first circuit (22) samples the first signal and produces the digital signal from the first signal using the amplifier. A second output of the second circuit (24) is coupled to the amplifier (28). The second circuit (24) samples and scales the analog signal via the amplifier (28) to produce the first signal within the signal range and cancels an offset of the first signal. The system and method reduce power consumption and save device area.
摘要翻译： 提供一种用于将模拟信号转换为数字信号的系统和方法，包括：具有信号范围的第一电路（22）和用于接收第一信号的输入端;以及第二电路（24），其具有接收模拟信号的输入端和 耦合到第一电路的输入的第一输出。 第一电路（22）包括放大器（28）。 第一电路（22）使用放大器从第一信号采样第一信号并产生数字信号。 第二电路（24）的第二输出耦合到放大器（28）。 第二电路（24）经由放大器（28）对模拟信号进行采样和缩放，以在信号范围内产生第一信号，并消除第一信号的偏移。 该系统和方法降低功耗并节省设备面积。
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公开(公告)号：US07190279B2
公开(公告)日：2007-03-13
申请号：US11063957
申请日：2005-02-22
CPC分类号： G08B1/08
摘要： A light modulation system as described herein can be incorporated into a personal or portable electronic apparatus such as a cellular telephone, a digital music player, or the like. The light modulation system controls the activation of light elements, such as light emitting diodes, of the host electronic apparatus in response to one or more analog audio signals available at the host electronic apparatus. The analog audio signals may be obtained from any suitable analog audio path or source in the host electronic apparatus. The light modulation system is compact, inexpensive to implement, and need not rely on digital signal processors for operation.
摘要翻译： 如本文所述的光调制系统可以并入到诸如蜂窝电话，数字音乐播放器等的个人或便携式电子设备中。 光调制系统响应于在主机电子设备处可用的一个或多个模拟音频信号来控制主机电子设备的光元件（例如发光二极管）的激活。 模拟音频信号可以从主机电子设备中的任何合适的模拟音频路径或源获得。 光调制系统紧凑，实施成本低廉，不需要依靠数字信号处理器进行操作。
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公开(公告)号：US07064700B1
公开(公告)日：2006-06-20
申请号：US11154405
申请日：2005-06-15
申请人： Douglas A. Garrity , Brandt Braswell , Thierry Cassagnes , Christopher J. Cavanagh , Mohammad Nlzam U Kablr , David R. LoCascio
发明人： Douglas A. Garrity , Brandt Braswell , Thierry Cassagnes , Christopher J. Cavanagh , Mohammad Nlzam U Kablr , David R. LoCascio
IPC分类号： H03M1/12
CPC分类号： H03M1/1225 , H03M1/146
摘要： A pipelined analog to digital converter (“ADC”) as described herein is capable of processing two or more input channels. The analog input voltages from the multiple channels are concurrently sampled (every other clock phase) using isolated input stages. The outputs of the input stages are concurrently sampled (every other clock phase) by a delay/holding and synchronization (“DHS”) stage. The DHS stage processes the samples using a double sampling technique, generates residual voltage samples (every clock phase), and generates digital outputs for the multiple channels in an alternating manner. The DHS stage provides equal input loading for the input stages, which enhances the performance of the ADC.
摘要翻译： 如本文所述的流水线模数转换器（“ADC”）能够处理两个或更多个输入通道。 来自多个通道的模拟输入电压使用隔离输入级同时采样（每隔一个时钟相位）。 输入级的输出通过延迟/保持和同步（“DHS”）级同时采样（每隔一个时钟相位）。 DHS级使用双重采样技术处理样品，产生残余电压采样（每个时钟相位），并以交替方式为多个通道生成数字输出。 DHS级为输入级提供相等的输入负载，增强了ADC的性能。
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7.发明授权Current reduction in a single stage cyclic analog to digital converter with variable resolution 有权具有可变分辨率的单级循环模数转换器的电流降低公开(公告)号：US08264393B2
公开(公告)日：2012-09-11
申请号：US12833597
申请日：2010-07-09
IPC分类号： H03M1/34
摘要： A converter (200) adapted to convert an analog input signal into a digital output signal includes an analog input terminal (205) for receiving the analog input signal, a Redundant Signed Digit (RSD) stage (210) coupled to the analog input terminal, and a digital section (220). The RSD stage is configured to receive the analog input signal at the analog input terminal, produce a first number of bits at a digital output from the analog input signal during a first half of a first clock cycle, provide a residual feedback signal of the analog input signal at the analog input terminal during a second half of the first clock cycle, and produce a second number of bits at the digital output from the residual feedback signal during a first half of a second clock cycle, the second number of bits less than the first number of bits.
摘要翻译： 适于将模拟输入信号转换为数字输出信号的A转换器（200）包括用于接收模拟输入信号的模拟输入端（205），耦合到模拟输入端的冗余有符号（RSD）级（210） 和数字部分（220）。 RSD级被配置为在模拟输入端接收模拟输入信号，在第一时钟周期的前半部分期间，从模拟输入信号的数字输出产生第一位数，提供模拟量的残留反馈信号 在第一时钟周期的后半段期间在模拟输入端子处输入信号，并且在第二时钟周期的前半部分期间从剩余反馈信号在数字输出处产生第二数量的位，第二个位数小于 第一位数。
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8.发明申请VEHICLE-BORNE RADAR SYSTEMS WITH CONTINUOUS-TIME, SIGMA DELTA ANALOG-TO-DIGITAL CONVERTERS, AND METHODS OF THEIR OPERATION 审中-公开具有连续时间的车载雷达雷达系统，SIGMA DELTA模拟数字转换器及其操作方法公开(公告)号：US20130314271A1
公开(公告)日：2013-11-28
申请号：US13480977
申请日：2012-05-25
CPC分类号： G01S13/34 , G01S7/352 , G01S13/931 , G01S2013/9314 , G01S2013/9321 , G01S2013/9325 , G01S2013/9332 , G01S2013/9342 , G01S2013/9346 , G01S2013/9375 , G01S2013/9378 , G01S2013/9385 , H03M3/424 , H03M3/448 , H03M3/452 , H03M3/454
摘要： Embodiments of vehicle-borne radar systems and methods of their operation are provided. The vehicle-borne radar system includes a transmit path and a first receive path. The transmit path is capable of producing a signal for transmission over an air interface (e.g., a frequency modulated continuous wave (FMCW) signal). The receive path includes a continuous-time (CT) sigma delta analog-to-digital converter (ADC), and the receive path is capable of receiving a reflected version of the signal from the air interface, and converting the reflected version along the receive path into a sequence of digital samples using the CT sigma delta ADC. In an embodiment, the transmit path and the receive path are integrated onto a single integrated circuit.
摘要翻译： 提供车载雷达系统的实施例及其操作方法。 车载雷达系统包括发射路径和第一接收路径。 发射路径能够产生用于通过空中接口传输的信号（例如，调频连续波（FMCW）信号）。 接收路径包括连续时间（CT）Σ-Δ模数转换器（ADC），并且接收路径能够从空中接口接收信号的反射版本，并沿接收器转换反射版本 使用CT西格玛Delta ADC的数字采样序列。 在一个实施例中，发射路径和接收路径被集成到单个集成电路上。
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9.发明申请CORRELATED-LEVEL-SHIFTING AND CORRELATED-DOUBLE-SAMPLING SWITCHED-CAPACITOR GAIN STAGES, SYSTEMS IMPLEMENTING THE GAIN STAGES, AND METHODS OF THEIR OPERATION 有权相关水平和相关双重采样开关电容器增益级别，实现增益级别的系统及其运行方法公开(公告)号：US20120249237A1
公开(公告)日：2012-10-04
申请号：US13075956
申请日：2011-03-30
IPC分类号： H03G3/20
CPC分类号： H03F3/005 , H03F3/45475 , H03F3/45986 , H03G1/0094
摘要： Embodiments of apparatus and methods for applying a gain to an input signal are provided. An embodiment of a switched-capacitor gain stage circuit includes an input node, an output node, an operational amplifier, a correlated-double-sampling portion, a correlated-level-shifting portion, and a switching configuration. The operational amplifier has a first amplifier input, a second amplifier input, and an amplifier output. The correlated-double-sampling portion includes a plurality of sampling capacitors arranged in parallel and selectively coupled between the input node and a central node, and an offset storage capacitor including a first terminal coupled to the first amplifier input. The correlated-level-shifting portion includes a correlated-level-shifting capacitor including a first terminal coupled to the output node. The switching configuration has multiple switches that are controllable sequentially to place the gain stage circuit in a sampling state, an approximate output voltage storage state, a level shifting and gain state, and an output state.
摘要翻译： 提供了用于向输入信号施加增益的装置和方法的实施例。 开关电容器增益级电路的实施例包括输入节点，输出节点，运算放大器，相关双采样部分，相关电平转换部分和切换配置。 运算放大器具有第一放大器输入，第二放大器输入和放大器输出。 相关双采样部分包括并联布置并选择性地耦合在输入节点和中心节点之间的多个采样电容器和包括耦合到第一放大器输入的第一端子的偏移存储电容器。 相关电平移位部分包括相关电平移位电容器，其包括耦合到输出节点的第一端子。 开关配置具有可以顺序控制的多个开关，以将增益级电路置于采样状态，近似输出电压存储状态，电平移位和增益状态以及输出状态。
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10.发明申请CURRENT REDUCTION IN A SINGLE STAGE CYCLIC ANALOG TO DIGITAL CONVERTER WITH VARIABLE RESOLUTION 有权在单阶段循环模式下的电流减少到具有可变分辨率的数字转换器公开(公告)号：US20120007762A1
公开(公告)日：2012-01-12
申请号：US12833597
申请日：2010-07-09
IPC分类号： H03M1/34
摘要： A converter (200) adapted to convert an analog input signal into a digital output signal includes an analog input terminal (205) for receiving the analog input signal, a Redundant Signed Digit (RSD) stage (210) coupled to the analog input terminal, and a digital section (220). The RSD stage is configured to receive the analog input signal at the analog input terminal, produce a first number of bits at a digital output from the analog input signal during a first half of a first clock cycle, provide a residual feedback signal of the analog input signal at the analog input terminal during a second half of the first clock cycle, and produce a second number of bits at the digital output from the residual feedback signal during a first half of a second clock cycle, the second number of bits less than the first number of bits.
摘要翻译： 适于将模拟输入信号转换为数字输出信号的A转换器（200）包括用于接收模拟输入信号的模拟输入端（205），耦合到模拟输入端的冗余有符号（RSD）级（210） 和数字部分（220）。 RSD级被配置为在模拟输入端接收模拟输入信号，在第一时钟周期的前半部分期间，从模拟输入信号的数字输出产生第一位数，提供模拟量的残留反馈信号 在第一时钟周期的后半段期间在模拟输入端子处输入信号，并且在第二时钟周期的前半部分期间，从剩余反馈信号在数字输出处产生第二数量的位，第二个位数小于 第一位数。
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