公开(公告)号：US07064700B1

公开(公告)日：2006-06-20

申请号：US11154405

申请日：2005-06-15

申请人： Douglas A. Garrity ,  Brandt Braswell ,  Thierry Cassagnes ,  Christopher J. Cavanagh ,  Mohammad Nlzam U Kablr ,  David R. LoCascio

发明人： Douglas A. Garrity ,  Brandt Braswell ,  Thierry Cassagnes ,  Christopher J. Cavanagh ,  Mohammad Nlzam U Kablr ,  David R. LoCascio

IPC分类号： H03M1/12

CPC分类号： H03M1/1225 ,  H03M1/146

摘要： A pipelined analog to digital converter (“ADC”) as described herein is capable of processing two or more input channels. The analog input voltages from the multiple channels are concurrently sampled (every other clock phase) using isolated input stages. The outputs of the input stages are concurrently sampled (every other clock phase) by a delay/holding and synchronization (“DHS”) stage. The DHS stage processes the samples using a double sampling technique, generates residual voltage samples (every clock phase), and generates digital outputs for the multiple channels in an alternating manner. The DHS stage provides equal input loading for the input stages, which enhances the performance of the ADC.

摘要翻译： 如本文所述的流水线模数转换器（“ADC”）能够处理两个或更多个输入通道。 来自多个通道的模拟输入电压使用隔离输入级同时采样（每隔一个时钟相位）。 输入级的输出通过延迟/保持和同步（“DHS”）级同时采样（每隔一个时钟相位）。 DHS级使用双重采样技术处理样品，产生残余电压采样（每个时钟相位），并以交替方式为多个通道生成数字输出。 DHS级为输入级提供相等的输入负载，增强了ADC的性能。