公开(公告)号：US20190056760A1

公开(公告)日：2019-02-21

申请号：US15678811

申请日：2017-08-16

Applicant: Oracle International Corporation

Inventor： Dabin Zhang ,  Philip P. Kwan ,  Zuxu Qin

IPC: G06F1/10 ,  H03L7/18 ,  H03K19/0185

Abstract: A clock distribution network and method of distributing a clock signal is disclosed. In one embodiment, a clock distribution network is coupled to at least a first circuit. The clock distribution network includes a clock source configured to generate a differential clock signal and provide it to a current mode logic (CML) driver. The CML driver is configured to transmit the clock signal over a differential signal path. A CML receiver is coupled to receive the clock signal via the differential signal path.

公开(公告)号：US10712769B2

公开(公告)日：2020-07-14

申请号：US15678811

申请日：2017-08-16

Applicant: Oracle International Corporation

Inventor： Dabin Zhang ,  Philip P. Kwan ,  Zuxu Qin

IPC: G06F1/10 ,  H03K19/0185 ,  H03F3/45 ,  H03K5/15

Abstract: A clock distribution network and method of distributing a clock signal is disclosed. In one embodiment, a clock distribution network is coupled to at least a first circuit. The clock distribution network includes a clock source configured to generate a differential clock signal and provide it to a current mode logic (CML) driver. The CML driver is configured to transmit the clock signal over a differential signal path. A CML receiver is coupled to receive the clock signal via the differential signal path.

公开(公告)号：US20170222796A1

公开(公告)日：2017-08-03

申请号：US15012518

申请日：2016-02-01

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： Ben Li Chen ,  Zuxu Qin ,  Nima Edelkhani

IPC: H04L7/033

CPC classification number: H04L7/0337 ,  G01R25/005 ,  H03K5/151 ,  H03K5/1565 ,  H03K23/58 ,  H04L7/0025 ,  H04L7/0037

Abstract: Embodiments include systems and methods for detecting and correcting phased clock error (PCE) in phased clock circuits (e.g., in context of serializer/deserializer (SERDES) transmission (TX) clock circuits). For example, phased input clock signals can be converted into unit interval (UI) clocks, which can be combined to form an output clock signal. PCE in the output clock signal can be detected by digitally sampling the UI clocks to characterize their respective clock pulse widths, and comparing the respective clock pulse widths (i.e., PCE in the output clock signal can result from pulse width differences in UI clocks). Delay can be applied to one or more UI clock generation paths to shift UI clock pulse transitions, thereby adjusting output clock pulse widths to correct for the detected PCE. Approaches described herein can achieve PCE detection over a wide error range and can achieve error correction with small resolution.

公开(公告)号：US20150015315A1

公开(公告)日：2015-01-15

申请号：US13937424

申请日：2013-07-09

Applicant: Oracle International Corporation

Inventor： Zuxu Qin ,  Dawei Huang ,  Deqiang Song ,  Jianghui Su ,  Baoqing Huang ,  Yan Yan

IPC: H03K7/08

CPC classification number: H03K7/08 ,  H03K5/1565

Abstract: A method and apparatus for duty cycle distortion compensation is disclosed. In one embodiment, an integrated circuit includes a differential signal transmitter having a main data path and a compensation data path. The main data path includes a first and second differential driver circuits each having output terminals coupled to a differential output. A transmission controller is configured to transmit data into the main and compensation data paths, the data corresponding to pairs of sequentially transmitted bits including an odd data bit followed by an even data bit, and further configured to determine respective duty cycle widths for each of the odd and even data bits as received by the transmission controller. The transmission controller is configured to cause the first and second driver circuits to equalize the respective duty cycle widths of the odd and even data bits, as transmitted, based their respective duty cycle widths as received.

Abstract translation: 公开了一种用于占空比失真补偿的方法和装置。 在一个实施例中，集成电路包括具有主数据路径和补偿数据路径的差分信号发送器。 主数据路径包括具有耦合到差分输出的输出端的第一和第二差分驱动器电路。 发送控制器被配置为将数据发送到主和补偿数据路径中，数据对应于顺序发送的比特对，包括奇数数据位，后跟偶数数据位，并进一步被配置为确定各个占空比宽度 由传输控制器接收的奇数和偶数数据位。 传输控制器被配置为使得第一和第二驱动器电路基于其所接收的各自的占空比宽度来均衡发送的奇数和偶数数据位的相应占空比宽度。

公开(公告)号：US20190104088A1

公开(公告)日：2019-04-04

申请号：US15722349

申请日：2017-10-02

Applicant: Oracle International Corporation

Inventor： Zuxu Qin ,  Baoqing Huang ,  Dawei Huang ,  Kuai Yin ,  Maoqing Yao ,  Philip Kwan

IPC: H04L12/935 ,  H04L9/06 ,  B23P19/04

Abstract: Embodiments include systems and methods for transmitting data over high-speed data channels in context of serializer/deserializer circuits. Some embodiments include a novel full-rate source-series-terminated (SST) transmitter driver architecture with output charge sharing isolation. Certain implementations have a programmable floating tap (e.g., in addition to standard taps) with both positive and negative FIR values and cursor reduction, which can help achieve large FIR range and high channel equalization capability. Some embodiments operate with multi-phase clocking having phased clock error correction, which can facilitate operation with low-jitter and low-DCD clocks. Some implementations also include novel output inductor structures that are disposed to partially overlap output interface bumps.

公开(公告)号：US09893878B1

公开(公告)日：2018-02-13

申请号：US15459715

申请日：2017-03-15

Applicant: Oracle International Corporation

Inventor： Long Kong ,  Ben Li Chen ,  Philip Kwan ,  Zuxu Qin ,  Dawei Huang

IPC: H04L27/152 ,  H04L7/033 ,  H03L7/089 ,  H03L7/099 ,  H03L7/081 ,  H04L7/00

CPC classification number: H04L1/20 ,  H03L7/08

Abstract: Embodiments include systems and methods for on-chip random jitter (RJ) measurement in a clocking circuit (e.g., in a phase-locked loop of a serializer/deserializer circuit). Some embodiments determine a reference delay code sweep window to capture at least a candidate RJ range of a feedback clock signal, the reference delay code sweep window comprising a sequence of reference delay codes. A distribution of one-scores can be computed over the reference delay code sweep window, so that the distribution indicates a relatively likelihood, for each reference delay code, of obtaining a ‘1’ sample when sampling the feedback clock signal according to the delayed clock signal (delayed by an amount according to the reference delay code). The distribution can be transformed into a time domain by computing code offset times for the reference delay codes. A RJ output can be computed as a function of the distribution in the time domain.

公开(公告)号：US09832013B2

公开(公告)日：2017-11-28

申请号：US15012518

申请日：2016-02-01

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： Ben Li Chen ,  Zuxu Qin ,  Nima Edelkhani

IPC: H04L7/033 ,  H04L7/04 ,  H04L7/00 ,  G01R25/00 ,  H03K5/156 ,  H03K5/151 ,  H03K23/58

CPC classification number: H04L7/0337 ,  G01R25/005 ,  H03K5/151 ,  H03K5/1565 ,  H03K23/58 ,  H04L7/0025 ,  H04L7/0037

Abstract: Embodiments include systems and methods for detecting and correcting phased clock error (PCE) in phased clock circuits (e.g., in context of serializer/deserializer (SERDES) transmission (TX) clock circuits). For example, phased input clock signals can be converted into unit interval (UI) clocks, which can be combined to form an output clock signal. PCE in the output clock signal can be detected by digitally sampling the UI clocks to characterize their respective clock pulse widths, and comparing the respective clock pulse widths (i.e., PCE in the output clock signal can result from pulse width differences in UI clocks). Delay can be applied to one or more UI clock generation paths to shift UI clock pulse transitions, thereby adjusting output clock pulse widths to correct for the detected PCE. Approaches described herein can achieve PCE detection over a wide error range and can achieve error correction with small resolution.

公开(公告)号：US10257121B1

公开(公告)日：2019-04-09

申请号：US15722349

申请日：2017-10-02

Applicant: Oracle International Corporation

Inventor： Zuxu Qin ,  Baoqing Huang ,  Dawei Huang ,  Kuai Yin ,  Maoqing Yao ,  Philip Kwan

IPC: H04L9/06 ,  B23P19/04 ,  H04L12/935

Abstract: Embodiments include systems and methods for transmitting data over high-speed data channels in context of serializer/deserializer circuits. Some embodiments include a novel full-rate source-series-terminated (SST) transmitter driver architecture with output charge sharing isolation. Certain implementations have a programmable floating tap (e.g., in addition to standard taps) with both positive and negative FIR values and cursor reduction, which can help achieve large FIR range and high channel equalization capability. Some embodiments operate with multi-phase clocking having phased clock error correction, which can facilitate operation with low-jitter and low-DCD clocks. Some implementations also include novel output inductor structures that are disposed to partially overlap output interface bumps.

公开(公告)号：US10135643B1

公开(公告)日：2018-11-20

申请号：US15655034

申请日：2017-07-20

Applicant: Oracle International Corporation

Inventor： Long Kong ,  Ranjan Vaish ,  Muthukumar Vairavan ,  Zuxu Qin

IPC: H03H7/30 ,  H03H7/40 ,  H03K5/159 ,  H04L25/03

Abstract: An embodiment includes a first feedback tap, a second feedback tap, and a summation circuit. The summation circuit may include a first load and a second load coupled to each other at an internal circuit node, and coupled in series between a power supply node and an output node. The summation circuit may be configured to receive, via a serial communication link, an input signal indicative of a series of data symbols, and to generate an output voltage level on the output node based upon a current data symbol. The first feedback tap, coupled to the output node, may be configured to sink a first current from the output node based upon a first previously received data symbol. The second feedback tap, coupled to an intermediate circuit node, may be configured to sink a second current from the intermediate circuit node based upon a second previously received data symbol.

公开(公告)号：US09036757B1

公开(公告)日：2015-05-19

申请号：US14493652

申请日：2014-09-23

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： Jianghui Su ,  Francis Schumacher ,  Zuxu Qin ,  Dawei Huang

IPC: H04L7/00

CPC classification number: H04L7/10 ,  H04L7/0062

Abstract: Embodiments include systems and methods for applying post-cursor locking point adjustment to an at-rate clock data recovery (CDR) system. Some embodiments operate in context of a CDR circuit of a serializer/deserializer (SERDES). In one embodiment, a training routine is used to determine an optimal post-cursor target level. Increasing or decreasing the post-cursor target level can cause the CDR clocking to shift right or left, which can be seen as a shift of the channel impulse response with respect to the CDR sampling locations. In some implementations, the post-cursor can be locked to the determined target level. In other implementations, the determined target level can be compared to a fully-adapted post-cursor to tune adaptations performed by transmitter and/or receiver equalizers.

Abstract translation: 实施例包括用于将速度锁定点调整应用于速率时钟数据恢复（CDR）系统的系统和方法。 一些实施例在串行器/解串器（SERDES）的CDR电路的上下文中操作。 在一个实施例中，使用训练例程来确定最佳的后视标目标水平。 增加或减少后视标目标水平可能导致CDR时钟向右或向左移动，这可以被看作是信道脉冲响应相对于CDR采样位置的移位。 在一些实现中，后视标可以被锁定到确定的目标级别。 在其他实施方式中，可以将确定的目标水平与完全适配的后置光标进行比较，以调谐由发射机和/或接收机均衡器执行的适配。