-
公开(公告)号：US20170222796A1
公开(公告)日：2017-08-03
申请号：US15012518
申请日：2016-02-01
Applicant: ORACLE INTERNATIONAL CORPORATION
Inventor： Ben Li Chen , Zuxu Qin , Nima Edelkhani
IPC: H04L7/033
CPC classification number: H04L7/0337 , G01R25/005 , H03K5/151 , H03K5/1565 , H03K23/58 , H04L7/0025 , H04L7/0037
Abstract: Embodiments include systems and methods for detecting and correcting phased clock error (PCE) in phased clock circuits (e.g., in context of serializer/deserializer (SERDES) transmission (TX) clock circuits). For example, phased input clock signals can be converted into unit interval (UI) clocks, which can be combined to form an output clock signal. PCE in the output clock signal can be detected by digitally sampling the UI clocks to characterize their respective clock pulse widths, and comparing the respective clock pulse widths (i.e., PCE in the output clock signal can result from pulse width differences in UI clocks). Delay can be applied to one or more UI clock generation paths to shift UI clock pulse transitions, thereby adjusting output clock pulse widths to correct for the detected PCE. Approaches described herein can achieve PCE detection over a wide error range and can achieve error correction with small resolution.
-
公开(公告)号：US09832013B2
公开(公告)日：2017-11-28
申请号：US15012518
申请日：2016-02-01
Applicant: ORACLE INTERNATIONAL CORPORATION
Inventor： Ben Li Chen , Zuxu Qin , Nima Edelkhani
CPC classification number: H04L7/0337 , G01R25/005 , H03K5/151 , H03K5/1565 , H03K23/58 , H04L7/0025 , H04L7/0037
Abstract: Embodiments include systems and methods for detecting and correcting phased clock error (PCE) in phased clock circuits (e.g., in context of serializer/deserializer (SERDES) transmission (TX) clock circuits). For example, phased input clock signals can be converted into unit interval (UI) clocks, which can be combined to form an output clock signal. PCE in the output clock signal can be detected by digitally sampling the UI clocks to characterize their respective clock pulse widths, and comparing the respective clock pulse widths (i.e., PCE in the output clock signal can result from pulse width differences in UI clocks). Delay can be applied to one or more UI clock generation paths to shift UI clock pulse transitions, thereby adjusting output clock pulse widths to correct for the detected PCE. Approaches described herein can achieve PCE detection over a wide error range and can achieve error correction with small resolution.
-
公开(公告)号：US09281971B1
公开(公告)日：2016-03-08
申请号：US14618279
申请日：2015-02-10
Applicant: ORACLE INTERNATIONAL CORPORATION
Inventor： Nima Edelkhani
CPC classification number: H04L25/03057 , H04L1/203 , H04L1/242
Abstract: Embodiments include systems and methods for determining link margins of data communications channels in a communications system. For example, an integrated circuit includes a large number of input/output (I/O) channels, each with a respective receiver system. The receiver system can include equalizer subsystems, that attempt to adapt to their respective channels (e.g., to eliminate inter-symbol interference). Embodiments manipulate filter tap weights in the equalizer subsystems to controllably close its respective data eye until a failure region is detected, indicating that a threshold I/O error rate has been exceeded. Thus, for each channel, the filter tap weights can be allowed to fully adjust to identify fully adapted values, and they can be forced into a failure region to identify failure region values. A link margin for each channel can be derived for each channel according to the difference between the fully adapted and failure region values of the filter tap weights.
Abstract translation: 实施例包括用于确定通信系统中数据通信信道的链路余量的系统和方法。 例如，集成电路包括大量输入/输出（I / O）通道，每个通道具有相应的接收器系统。 接收机系统可以包括均衡器子系统，其尝试适应它们各自的信道（例如，消除符号间干扰）。 实施例操纵均衡器子系统中的滤波器抽头权重以可控地关闭其相应的数据眼睛，直到检测到故障区域，指示已经超过了阈值I / O错误率。 因此，对于每个通道，可以允许滤波器抽头权重进行完全调整以识别完全适应的值，并且可以将它们强制进入故障区域以识别故障区域值。 可以根据滤波器抽头权重的完全适应和故障区域值之间的差异为每个通道导出每个通道的链接余量。
-
-
Search Results
3
records
(took 0.028 seconds)
