公开(公告)号：US12080705B2

公开(公告)日：2024-09-03

申请号：US17609783

申请日：2019-07-12

申请人： Mitsubishi Electric Corporation

发明人： Kenji Hamada ,  Kazuya Konishi ,  Kotaro Kawahara

IPC分类号： H01L27/06 ,  H01L29/06 ,  H01L29/66 ,  H01L29/739

CPC分类号： H01L27/0629 ,  H01L29/0696 ,  H01L29/66333 ,  H01L29/7394

摘要： In order to improve energization capacity, minority carrier injection efficiency is increased. In a semiconductor device, an IGBT includes a first drift layer, a collector region, a base region, an emitter region, an insulating film, a gate electrode, and a first high carrier lifetime region formed at a position closer to the collector region than the base region and having a longer carrier lifetime than the first drift layer. An FWD includes a second drift layer, an anode region, and a second high carrier lifetime region formed at a position closer to the anode region than a lower surface of the second drift layer and having a longer carrier lifetime than the second drift layer.

公开(公告)号：US11049931B2

公开(公告)日：2021-06-29

申请号：US16717486

申请日：2019-12-17

申请人： Mitsubishi Electric Corporation

发明人： Yutaka Fukui ,  Katsutoshi Sugawara ,  Shiro Hino ,  Kazuya Konishi ,  Kohei Adachi

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/36 ,  H01L29/417 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78 ,  H01L21/02 ,  H01L21/04 ,  H01L23/544 ,  H01L29/66

摘要： A gate connection layer (14) includes a portion placed on an outer trench (TO) with a gate insulating film (7) being interposed. A first main electrode (10) includes a main contact (CS) electrically connected to a well region (4) and a first impurity region (5) within an active region (30), and an outer contact (CO) being spaced away from the active region (30) and in contact with a bottom face of the outer trench (TO). A trench-bottom field relaxing region (13) is provided in a drift layer (3). A trench-bottom high-concentration region (18) has an impurity concentration higher than that of the trench-bottom field relaxing region (13), is provided on the trench-bottom field relaxing region (13), and extends from a position where it faces the gate connection layer (14) with the gate insulating film (7) being interposed, to a position where it is in contact with the outer contact (CO) of the first main electrode (10).

公开(公告)号：US11777021B2

公开(公告)日：2023-10-03

申请号：US17409210

申请日：2021-08-23

申请人： Mitsubishi Electric Corporation

发明人： Kazuya Konishi ,  Koichi Nishi ,  Tetsuya Nitta

IPC分类号： H01L29/739 ,  H01L29/10

CPC分类号： H01L29/7397 ,  H01L29/1095

摘要： A semiconductor device includes: a carrier stored layer; an upper-stage active portion disposed on a first insulating film along an inner wall of an upper portion of a trench penetrating the carrier stored layer, the upper-stage active portion being upper-stage polysilicon connected to a gate electrode; and lower-stage polysilicon disposed on a second insulating film along an inner wall of a lower portion of the trench, the lower-stage polysilicon provided with a third insulating film disposed between the upper-stage active portion and the lower-stage polysilicon. The lower end of the upper-stage active portion is positioned below the lower end of the carrier stored layer.

公开(公告)号：US11158704B2

公开(公告)日：2021-10-26

申请号：US16090784

申请日：2017-01-18

申请人： Mitsubishi Electric Corporation

发明人： Kohei Adachi ,  Katsutoshi Sugawara ,  Yutaka Fukui ,  Rina Tanaka ,  Kazuya Konishi

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L29/12 ,  H01L29/10 ,  H02M1/08 ,  H02M7/5387 ,  H02P27/08

摘要： A semiconductor device including: a trench gate; a trench-bottom protecting layer of a second conductivity type provided in a semiconductor layer of a first conductivity type while contacting a bottom of trenches; and a depletion suppressing layer of the first conductivity type provided between adjacent trench-bottom protecting layers, wherein the depletion suppressing layer includes an intermediate point that is horizontally equidistant to the adjacent trench-bottom protecting layers and is formed of a size to contact neither the trenches nor the trench-bottom protecting layers, and an impurity concentration of the depletion suppressing layer is set higher than an impurity concentration of the semiconductor layer.

公开(公告)号：US20190226118A1

公开(公告)日：2019-07-25

申请号：US16375455

申请日：2019-04-04

申请人： MITSUBISHI ELECTRIC CORPORATION

发明人： Yu Nakamura ,  Kazuya Konishi

IPC分类号： C30B25/20 ,  H01L21/02 ,  H01L21/205 ,  C30B25/18 ,  C30B29/36 ,  H01L29/16 ,  H01L29/08 ,  H01L29/861 ,  H01L29/78 ,  H01L29/36

摘要： A silicon carbide epitaxial substrate includes a silicon carbide single-crystal substrate of one conductivity type, a first silicon carbide layer of the above-mentioned one conductivity type, a second silicon carbide layer of the above-mentioned one conductivity type, and a third silicon carbide layer of the above-mentioned one conductivity type. The silicon carbide single-crystal substrate has first impurity concentration. The first silicon carbide layer is provided on the silicon carbide single-crystal substrate, and has second impurity concentration that is lower than the first impurity concentration. The second silicon carbide layer is provided on the first silicon carbide layer, and has third impurity concentration that is higher than the first impurity concentration. The third silicon carbide layer is provided on the second silicon carbide layer, and has fourth impurity concentration that is lower than the second impurity concentration.

公开(公告)号：US12020935B2

公开(公告)日：2024-06-25

申请号：US17563603

申请日：2021-12-28

申请人： Mitsubishi Electric Corporation

发明人： Koichi Nishi ,  Shinya Soneda ,  Kazuya Konishi

IPC分类号： H01L21/266 ,  H01L21/22 ,  H01L21/768

CPC分类号： H01L21/266 ,  H01L21/2225 ,  H01L21/76831

摘要： An object of the present disclosure is to reduce masks and to reduce the variation in the profile of an impurity layer in a semiconductor device. A method of manufacturing a semiconductor device includes a step (b) of forming a base layer on a first main surface side of a drift layer in an active region by implanting p-type impurity ions of using the first mask, a step of (c) of forming an emitter layer on the first main surface side of the base layer by implanting n-type impurity ions using the first mask, a step (d) of forming trenches after the steps (b) and (c), a step (e) of embedding a gate electrode inside the trenches, and a step (g) of converting a part of the emitter layer into a first contact layer by implanting the p-type impurity ions having a high dosage using a second mask.

公开(公告)号：US10774441B2

公开(公告)日：2020-09-15

申请号：US16375455

申请日：2019-04-04

申请人： MITSUBISHI ELECTRIC CORPORATION

发明人： Yu Nakamura ,  Kazuya Konishi

IPC分类号： H01L29/15 ,  H01L31/0312 ,  C30B25/20 ,  C30B29/36 ,  H01L29/36 ,  H01L29/78 ,  H01L29/861 ,  H01L29/08 ,  H01L29/16 ,  C30B25/18 ,  H01L21/02 ,  H01L29/66 ,  H01L21/205 ,  H01L29/06

摘要： A silicon carbide epitaxial substrate includes a silicon carbide single-crystal substrate of one conductivity type, a first silicon carbide layer of the above-mentioned one conductivity type, a second silicon carbide layer of the above-mentioned one conductivity type, and a third silicon carbide layer of the above-mentioned one conductivity type. The silicon carbide single-crystal substrate has first impurity concentration. The first silicon carbide layer is provided on the silicon carbide single-crystal substrate, and has second impurity concentration that is lower than the first impurity concentration. The second silicon carbide layer is provided on the first silicon carbide layer, and has third impurity concentration that is higher than the first impurity concentration. The third silicon carbide layer is provided on the second silicon carbide layer, and has fourth impurity concentration that is lower than the second impurity concentration.

公开(公告)号：US10243067B2

公开(公告)日：2019-03-26

申请号：US14567354

申请日：2014-12-11

申请人： Mitsubishi Electric Corporation

发明人： Kazuya Konishi ,  Yusuke Fukada ,  Atsushi Narazaki

IPC分类号： H01L29/739 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L21/762 ,  H01L21/761 ,  H01L21/265

摘要： A semiconductor device includes a first semiconductor layer on one main surface of a semiconductor substrate; a plurality of trench gates in the first semiconductor layer extending to reach the inside of the semiconductor substrate; a second semiconductor layer selectively provided in an upper portion of the first semiconductor layer between the trench gates; an isolation layer in contact with a side surface of the second semiconductor layer and extends in the first semiconductor; and a third semiconductor layer in the upper portion of the first semiconductor layer between the trench gates and has at least one side surface in contact with the trench gate. The isolation layer is between and separates the second semiconductor layer and the third semiconductor layer from each other and is formed to extend to the same depth as, or to a position deeper than the second semiconductor layer.

公开(公告)号：US09874596B2

公开(公告)日：2018-01-23

申请号：US14772304

申请日：2014-03-10

申请人： MITSUBISHI ELECTRIC CORPORATION

发明人： Shoyu Watanabe ,  Akihiro Koyama ,  Shigehisa Yamamoto ,  Yukiyasu Nakao ,  Kazuya Konishi

IPC分类号： G01R31/26 ,  H01L21/66 ,  H01L29/16 ,  H01L29/32 ,  H01L29/66 ,  H01L29/78 ,  G01R31/28 ,  H01L21/56

CPC分类号： G01R31/2632 ,  G01R31/2648 ,  G01R31/2855 ,  G01R31/2877 ,  H01L21/565 ,  H01L22/14 ,  H01L29/1608 ,  H01L29/32 ,  H01L29/66068 ,  H01L29/7805 ,  H01L2924/0002

摘要： The present invention provides a method for manufacturing silicon carbide semiconductor apparatus including a testing step of testing a PN diode for the presence or absence of stacking faults in a relatively short time and an energization test apparatus. The present invention sets the temperature of a bipolar semiconductor element at 150° C. or higher and 230° C. or lower, causes a forward current having a current density of 120 [A/cm2] or more and 400 [A/cm2] or less to continuously flow through the bipolar semiconductor element, calculates, in a case where a forward resistance of the bipolar semiconductor element through which the forward current flows reaches a saturation state, the degree of change in the forward resistance, and determines whether the calculated degree of change is smaller than a threshold value.

公开(公告)号：US12021118B2

公开(公告)日：2024-06-25

申请号：US15741591

申请日：2015-08-26

申请人： Mitsubishi Electric Corporation

发明人： Kazuya Konishi ,  Yusuke Fukada ,  Ryu Kamibaba ,  Mariko Umeyama ,  Atsushi Narazaki ,  Masayoshi Tarutani

IPC分类号： H01L29/06 ,  H01L27/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/20 ,  H01L29/40 ,  H01L29/739 ,  H01L29/78

CPC分类号： H01L29/0696 ,  H01L27/0664 ,  H01L29/1095 ,  H01L29/1602 ,  H01L29/407 ,  H01L29/7397 ,  H01L29/7805 ,  H01L29/7813 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/2003

摘要： Included are a semiconductor substrate, an emitter electrode formed on the semiconductor substrate, a gate electrode formed on the semiconductor substrate, a source layer of a first conductivity type formed on the semiconductor substrate, a base layer of a second conductivity type formed on the semiconductor substrate, a collector electrode formed under the semiconductor substrate, a plurality of active trench gates formed on a top-surface side of the semiconductor substrate and connected to the gate electrode, and a plurality of dummy trench gates formed on the top-surface side of the semiconductor substrate and not connected to the gate electrode. First structures, each including three or more of the active trench gates arranged side by side, and second structures, each including three or more of the dummy trench gates arranged side by side, are alternately provided.