公开(公告)号：US11011378B2

公开(公告)日：2021-05-18

申请号：US16459079

申请日：2019-07-01

Applicant: Micron Technology, Inc.

Inventor： Yiping Wang ,  Caizhi Xu ,  Pengyuan Zheng ,  Ying Rui ,  Russell A. Benson ,  Yongjun J. Hu ,  Jaydeb Goswami

IPC: H01L21/033 ,  H01L27/108 ,  H01L21/308

Abstract: Systems, apparatuses, and methods related to atom implantation for reduction of compressive stress are described. An example method may include patterning a working surface of a semiconductor, the working surface having a hard mask material formed over a dielectric material and forming a material having a lower refractive index (RI), relative to a RI of the hard mask material, over the hard mask material. The method may further include implanting atoms through the lower RI material and into the hard mask material to reduce the compressive stress in the hard mask material.

公开(公告)号：US08846512B2

公开(公告)日：2014-09-30

申请号：US13936724

申请日：2013-07-08

Applicant: Micron Technology, Inc.

Inventor： Jaydeb Goswami

IPC: H01L21/22 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788 ,  H01L21/3215 ,  H01L27/115

CPC classification number: H01L21/28273 ,  H01L21/32155 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/7881

Abstract: Methods of incorporating impurities into materials can be useful in non-volatile memory devices as well as other integrated circuit devices. Various embodiments provide for incorporating impurities into a material using a mask.

Abstract translation: 将杂质掺入材料中的方法可用于非易失性存储器件以及其它集成电路器件。 各种实施例提供了使用掩模将杂质掺入材料中。

公开(公告)号：US20140010018A1

公开(公告)日：2014-01-09

申请号：US14021705

申请日：2013-09-09

Applicant: Micron Technology, Inc.

Inventor： Jaydeb Goswami

IPC: H01L27/11

CPC classification number: H01L27/1104 ,  B82Y10/00 ,  H01L21/28273 ,  H01L29/42332

Abstract: Methods, devices, and systems associated with charge storage structures in semiconductor devices are described herein. In one or more embodiments, a method of forming nanodots includes forming at least a portion of a charge storage structure over a material by reacting a single-source precursor and a reactant, where the single-source precursor includes a metal and a semiconductor.

Abstract translation: 本文描述了与半导体器件中的电荷存储结构相关联的方法，器件和系统。 在一个或多个实施方案中，形成纳米点的方法包括通过使单源前体和反应物反应而在材料上形成电荷存储结构的至少一部分，其中单源前体包括金属和半导体。

公开(公告)号：US11101274B2

公开(公告)日：2021-08-24

申请号：US16704657

申请日：2019-12-05

Applicant: Micron Technology, Inc.

Inventor： Clement Jacob ,  Vassil N. Antonov ,  Jaydeb Goswami ,  Albert Liao ,  Christopher W. Petz ,  Durai Vishak Nirmal Ramaswamy

IPC: H01L21/00 ,  H01L27/11507 ,  H01L21/02 ,  H01L49/02

Abstract: A ferroelectric capacitor comprises two conductive capacitor electrodes having ferroelectric material there-between. At least one of the capacitor electrodes comprise MxSiOy, where “M” is at least one of Ru, Ti, Ta, Co, Pt, Ir. Os, Mo, V, W, Sr, Re, Rh, Pd, La, Zn, In, Sn, and Nb. Other aspects, including method, are disclosed.

公开(公告)号：US09397105B2

公开(公告)日：2016-07-19

申请号：US14021705

申请日：2013-09-09

Applicant: Micron Technology, Inc.

Inventor： Jaydeb Goswami

IPC: H01L29/788 ,  H01L27/11 ,  B82Y10/00 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L27/1104 ,  B82Y10/00 ,  H01L21/28273 ,  H01L29/42332

Abstract: Methods, devices, and systems associated with charge storage structures in semiconductor devices are described herein. In one or more embodiments, a method of forming nanodots includes forming at least a portion of a charge storage structure over a material by reacting a single-source precursor and a reactant, where the single-source precursor includes a metal and a semiconductor.

Abstract translation: 本文描述了与半导体器件中的电荷存储结构相关联的方法，器件和系统。 在一个或多个实施方案中，形成纳米点的方法包括通过使单源前体和反应物反应而在材料上形成电荷存储结构的至少一部分，其中单源前体包括金属和半导体。

公开(公告)号：US20160118340A1

公开(公告)日：2016-04-28

申请号：US14941288

申请日：2015-11-13

Applicant: Micron Technology, Inc.

Inventor： Jaydeb Goswami ,  Allen McTeer

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/535

CPC classification number: H01L23/5226 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53266 ,  H01L23/53271 ,  H01L23/53295 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Devices and methods for providing low-resistance interconnects in a semiconductor device are provided. Specifically, one or more embodiments of the present invention relate to disposing a conductive material in a trench without disposing a resistive barrier material between the conductive material and the sidewalls of the trench so that the conductive material takes up the full width of the trench. For example, the trench may be disposed over one or more contacts made of a barrier material such as titanium nitride that also acts as a seed, and the conductive material may be grown on top of the titanium nitride to fill the trench.

Abstract translation: 提供了用于在半导体器件中提供低电阻互连的装置和方法。 具体地，本发明的一个或多个实施例涉及将导电材料设置在沟槽中而不在导电材料和沟槽的侧壁之间设置电阻阻挡材料，使得导电材料占据沟槽的整个宽度。 例如，沟槽可以设置在由阻挡材料制成的一个或多个触点上，例如氮化钛也可以作为种子，并且导电材料可以在氮化钛的顶部生长以填充沟槽。

公开(公告)号：US09142670B2

公开(公告)日：2015-09-22

申请号：US14274988

申请日：2014-05-12

Applicant: Micron Technology, Inc.

Inventor： Jaydeb Goswami

IPC: H01L21/00 ,  H01L29/78 ,  H01L21/3213 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/7831 ,  H01L21/32134 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

Abstract: Semiconductor devices including dual gate structures and methods of forming such semiconductor devices are disclosed. For example, semiconductor devices are disclosed that include a first gate stack that may include a first conductive gate structure formed from a first material, and a second gate stack that may include a dielectric structure formed from an oxide of the first material. For another example, methods including forming a high-K dielectric material layer over a semiconductor substrate, forming a first conductive material layer over the high-K dielectric material layer, oxidizing a portion of the first conductive material layer to convert the portion of the first conductive material layer to a dielectric material layer, and forming a second conductive material layer over both the conductive material layer and the dielectric material layer are also disclosed.

Abstract translation: 公开了包括双栅极结构的半导体器件和形成这种半导体器件的方法。 例如，公开了包括可以包括由第一材料形成的第一导电栅极结构的第一栅极堆叠和可以包括由第一材料的氧化物形成的电介质结构的第二栅极堆叠的半导体器件。 另一个实例是包括在半导体衬底上形成高K电介质材料层的方法，在高K电介质材料层上形成第一导电材料层，氧化第一导电材料层的一部分以转换第一 导电材料层到介电材料层，并且在导电材料层和介电材料层两者之上形成第二导电材料层。

公开(公告)号：US09099472B2

公开(公告)日：2015-08-04

申请号：US14063981

申请日：2013-10-25

Applicant: Micron Technology, Inc.

Inventor： Jaydeb Goswami ,  Hung Ming Tsai ,  Duane M. Goodner

IPC: H01L23/532 ,  C23C16/04 ,  H01L27/108 ,  H01L21/74 ,  H01L21/768

CPC classification number: H01L23/53252 ,  C23C16/045 ,  H01L21/743 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53266 ,  H01L27/10876 ,  H01L27/10891 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments include methods of forming conductive structures. An electrically conductive material may be deposited with a first deposition method. The first deposition method has a first deposition rate and forms a first portion of a conductive structure. A second portion of the conductive structure may be formed by depositing the electrically conductive material with a second deposition method having a second deposition rate. The second deposition rate may be different from the first deposition rate by at least about a factor of 3. In some embodiments, a region of the conductive structure is utilized as a transistor gate of a DRAM cell. Some embodiments include semiconductor constructions.

Abstract translation: 一些实施例包括形成导电结构的方法。 可以用第一沉积方法沉积导电材料。 第一沉积方法具有第一沉积速率并形成导电结构的第一部分。 导电结构的第二部分可以通过用具有第二沉积速率的第二沉积方法沉积导电材料来形成。 第二沉积速率可以不同于第一沉积速率至少约3倍。在一些实施例中，导电结构的区域用作DRAM单元的晶体管栅极。 一些实施例包括半导体结构。

公开(公告)号：US20140117302A1

公开(公告)日：2014-05-01

申请号：US13666744

申请日：2012-11-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jaydeb Goswami

IPC: H01L45/00

CPC classification number: H01L45/126 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/16

Abstract: A phase change memory cell includes a pair of electrodes having phase change material and heater material there-between. An electrically conductive thermal barrier material is between one of the electrodes and the heater material. Methods are disclosed.

Abstract translation: 相变存储单元包括一对在其之间具有相变材料和加热器材料的电极。 导电的热障材料位于电极之间和加热器材料之间。 公开了方法。

公开(公告)号：US08698173B2

公开(公告)日：2014-04-15

申请号：US13758401

申请日：2013-02-04

Applicant: Micron Technology, Inc.

Inventor： Jaydeb Goswami

IPC: H01L33/16

CPC classification number: H01L33/16 ,  H01L21/0237 ,  H01L21/02439 ,  H01L21/0245 ,  H01L21/02458 ,  H01L21/02494 ,  H01L21/02516 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/02647 ,  H01L33/007 ,  H01L33/20 ,  H01L33/32

Abstract: Solid state lighting devices with semi-polar or non-polar surfaces and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting device includes a substrate material having a substrate surface and an epitaxial silicon structure in direct contact with the substrate surface. The epitaxial silicon structure has a sidewall extending away from the substrate surface. The solid state lighting device also includes a semiconductor material on at least a portion of the sidewall of the epitaxial silicon structure. The semiconductor material has a semiconductor surface that is spaced apart from the substrate surface and is located on a semi-polar or non-polar crystal plane of the semiconductor material.

Abstract translation: 本文公开了具有半极性或非极性表面的固态照明装置和相关的制造方法。 在一个实施例中，固态照明装置包括具有衬底表面和与衬底表面直接接触的外延硅结构的衬底材料。 外延硅结构具有远离衬底表面延伸的侧壁。 固态照明装置还包括在外延硅结构的侧壁的至少一部分上的半导体材料。 半导体材料具有与衬底表面间隔开并位于半导体材料的半极性或非极性晶体平面上的半导体表面。