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    Semiconductor nitridation passivation
    2.
    发明授权
    Semiconductor nitridation passivation 有权

    公开(公告)号：US11189484B2

    公开(公告)日：2021-11-30

    申请号：US16723557

    申请日：2019-12-20

    Applicant: Micron Technology, Inc.

    Inventor： Russell A. Benson ,  Silvia Borsari ,  Vinay Nair ,  Ying Rui ,  Somik Mukherjee

    IPC: H01L21/02 ,  H01L21/3213 ,  H01L21/311

    Abstract: Methods, apparatuses, and systems related to a semiconductor nitridation passivation are described. An example method includes performing a dry etch process on a semiconductor structure on a wafer in a semiconductor fabrication process. The method further includes performing a dry strip process on the semiconductor structure. The method further includes performing a first wet strip clean process on the semiconductor. The method further includes performing a second wet strip clean process on the semiconductor. The method further includes performing a nitridation passivation on the semiconductor structure to avoid oxidization of the semiconductor structure. The method further performing a spacer material deposition on the semiconductor structure.

    Methods used in the fabrication of integrated circuitry
    4.
    发明授权
    Methods used in the fabrication of integrated circuitry 有权

    公开(公告)号：US10971500B2

    公开(公告)日：2021-04-06

    申请号：US16433966

    申请日：2019-06-06

    Applicant: Micron Technology, Inc.

    Inventor： Ying Rui ,  Tong Liu ,  Yi Fang Lee ,  Davide Colombo ,  Silvia Borsari ,  Austin Johnson

    IPC: H01L27/108 ,  H01L49/02 ,  H01L21/768 ,  H01L27/11502

    Abstract: A method used in fabrication of integrated circuitry comprises forming metal material outwardly of a substrate. At least a majority (i.e., up to and including 100%) of the metal material contains ruthenium in at least one of elemental-form, metal compound-form, or alloy-form. A masking material is formed outwardly of the ruthenium-containing metal material. The masking material comprises at least one of nine specifically enumerated materials or category of materials. The masking material is used as a mask while etching through an exposed portion of the ruthenium-containing metal material to form a feature of integrated circuitry that comprises the ruthenium-containing metal material.

    SEMICONDUCTOR NITRIDATION PASSIVATION
    5.
    发明申请
    SEMICONDUCTOR NITRIDATION PASSIVATION 有权

    公开(公告)号：US20210193460A1

    公开(公告)日：2021-06-24

    申请号：US16723557

    申请日：2019-12-20

    Applicant: Micron Technology, Inc.

    Inventor： Russell A. Benson ,  Silvia Borsari ,  Vinay Nair ,  Ying Rui ,  Somik Mukherjee

    IPC: H01L21/02 ,  H01L21/311 ,  H01L21/3213

    Abstract: Methods, apparatuses, and systems related to a semiconductor nitridation passivation are described. An example method includes performing a dry etch process on a semiconductor structure on a wafer in a semiconductor fabrication process. The method further includes performing a dry strip process on the semiconductor structure. The method further includes performing a first wet strip clean process on the semiconductor. The method further includes performing a second wet strip clean process on the semiconductor. The method further includes performing a nitridation passivation on the semiconductor structure to avoid oxidization of the semiconductor structure. The method further performing a spacer material deposition on the semiconductor structure.

    Memory Circuitry And Methods Used In Forming Memory Circuitry
    6.
    发明公开
    Memory Circuitry And Methods Used In Forming Memory Circuitry 审中-公开

    公开(公告)号：US20240224505A1

    公开(公告)日：2024-07-04

    申请号：US18527091

    申请日：2023-12-01

    Applicant: Micron Technology, Inc.

    Inventor： Jordan D. Greenlee ,  Ying Rui ,  Silvia Borsari ,  Prashant Raghu ,  Elisabeth Barr ,  Yen Ting Lin ,  Albert P. Chan ,  Martin Chen

    IPC: H10B12/00

    CPC classification number: H10B12/33 ,  H10B12/0335 ,  H10B12/05 ,  H10B12/482

    Abstract: A method used in forming memory circuitry comprises forming transistors individually comprising one source/drain region and another source/drain region. A channel region is between the one and the another source/drain regions. A conductive gate is operatively proximate the channel region. Digitline structures are formed that are individually directly electrically coupled to the another source/drain regions of multiple of the transistors. The digitline structures individually comprise a conductive digitline and an insulator material thereatop. The insulator material has a top. First insulating material is formed directly above the tops of the insulator material and laterally-over longitudinal sides of the digitline structures and covers across the one source/drain regions laterally-between immediately-adjacent of the digitline structures. Second insulating material is formed over the first insulating material. The second insulating material has a maximum vertical thickness directly above the digitline structures that is greater than its minimum lateral thickness over the longitudinal sides of the digitline structures. The first insulating material is etched through to expose the one source/drain regions. Storage elements are formed that are individually electrically coupled to individual of the one source/drain regions. Other embodiments, including structure, are disclosed.

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