公开(公告)号：US11417730B2

公开(公告)日：2022-08-16

申请号：US16986436

申请日：2020-08-06

Applicant: Micron Technology, Inc.

Inventor： Manuj Nahar ,  Vassil N. Antonov ,  Kamal M. Karda ,  Michael Mutch ,  Hung-Wei Liu ,  Jeffery B. Hull

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/04 ,  H01L21/02

Abstract: A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. The channel region is crystalline and comprises a plurality of vertically-elongated crystal grains that individually are directly against both of the top source/drain region and the bottom source/drain region. Other embodiments, including methods, are disclosed.

公开(公告)号：US20220093617A1

公开(公告)日：2022-03-24

申请号：US17027046

申请日：2020-09-21

Applicant: Micron Technology, Inc.

Inventor： Hung-Wei Liu ,  Vassil N. Antonov ,  Ashonita A. Chavan ,  Darwin Franseda Fan ,  Jeffery B. Hull ,  Anish A. Khandekar ,  Masihhur R. Laskar ,  Albert Liao ,  Xue-Feng Lin ,  Manuj Nahar ,  Irina V. Vasilyeva

IPC: H01L27/11514 ,  H01L27/11507 ,  H01L29/78 ,  H01L21/223 ,  H01L27/11597 ,  H01L27/1159 ,  H01L29/10 ,  H01L29/66

Abstract: A method of forming a vertical transistor comprising a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region comprises, in multiple time-spaced microwave annealing steps, microwave annealing at least the channel region. The multiple time-spaced microwave annealing steps reduce average concentration of elemental-form H in the channel region from what it was before start of the multiple time-spaced microwave annealing steps. The reduced average concentration of elemental-form H is 0.005 to less than 1 atomic percent. Structure embodiments are disclosed.

公开(公告)号：US20190198606A1

公开(公告)日：2019-06-27

申请号：US15855665

申请日：2017-12-27

Applicant: Micron Technology, Inc.

Inventor： Manuj Nahar ,  Vassil N. Antonov

IPC: H01L49/02 ,  H01L21/02

Abstract: A method used in forming at least a portion of at least one conductive capacitor electrode of a capacitor that comprises a pair of conductive capacitor electrodes having a capacitor insulator there-between comprises forming an insulative first material comprising an amorphous insulative metal oxide. The amorphous insulative metal oxide is reduced in a reducing-ambient to form a conductive second material from the insulative first material. Such reducing in the reducing-ambient both (a) removes oxygen from and changes the stoichiometry of the metal oxide, and (b) crystallizes the metal oxide into a crystalline state that is conductive.

公开(公告)号：US20220344468A1

公开(公告)日：2022-10-27

申请号：US17860325

申请日：2022-07-08

Applicant: Micron Technology, Inc.

Inventor： Manuj Nahar ,  Vassil N. Antonov ,  Kamal M. Karda ,  Michael Mutch ,  Hung-Wei Liu ,  Jeffery B. Hull

IPC: H01L29/08 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/78 ,  H01L29/04

Abstract: A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. The channel region is crystalline and comprises a plurality of vertically-elongated crystal grains that individually are directly against both of the top source/drain region and the bottom source/drain region. Other embodiments, including methods, are disclosed.

公开(公告)号：US20210343732A1

公开(公告)日：2021-11-04

申请号：US17377665

申请日：2021-07-16

Applicant: Micron Technology, Inc.

Inventor： Clement Jacob ,  Vassil N. Antonov ,  Jaydeb Goswami ,  Albert Liao ,  Christopher W. Petz ,  Durai Vishak Nirmal Ramaswamy

IPC: H01L27/11507 ,  H01L21/02 ,  H01L49/02

Abstract: A ferroelectric capacitor comprises two conductive capacitor electrodes having ferroelectric material there-between. At least one of the capacitor electrodes comprise MxSiOy, where “M” is at least one of Ru, Ti, Ta, Co, Pt, Ir, Os, Mo, V, W, Sr, Re, Rh, Pd, La, Zn, In, Sig, and Nb, Other aspects, including method, are disclosed.

公开(公告)号：US20160027642A1

公开(公告)日：2016-01-28

申请号：US14877677

申请日：2015-10-07

Applicant: Micron Technology, Inc.

Inventor： Vassil N. Antonov ,  Vishwanath Bhat

IPC: H01L21/02 ,  H01L21/3105 ,  H01L49/02

CPC classification number: H01L21/02356 ,  H01L21/02175 ,  H01L21/02186 ,  H01L21/3105 ,  H01L28/65

Abstract: A method of forming a capacitor includes depositing a dielectric metal oxide layer of a first phase to a thickness no greater than 75 Angstroms over an inner conductive capacitor electrode material. The first phase dielectric metal oxide layer has a k of at least 15. Conductive RuO2 is deposited over and into physical contact with the dielectric metal oxide layer. Then, the RuO2 and the dielectric metal oxide layer are annealed at a temperature below 500° C. The RuO2 in physical contact with the dielectric metal oxide during the annealing facilitates a change of the dielectric metal oxide layer from the first phase to a second crystalline phase having a higher k than the first phase. The annealed dielectric metal oxide layer is incorporated into a capacitor dielectric region of a capacitor construction. Other implementations are disclosed.

Abstract translation: 形成电容器的方法包括在内部导电电容器电极材料上沉积第一相的电介质金属氧化物层至不大于75埃的厚度。 第一相介电金属氧化物层的k至少为15.导电RuO 2沉积在物理接触介电金属氧化物层上。 然后，RuO 2和介电金属氧化物层在低于500℃的温度下退火。退火期间与电介质金属氧化物物理接触的RuO 2促进介电金属氧化物层从第一相到第二晶体的变化 相具有比第一相高的k。 退火的介质金属氧化物层被结合到电容器结构的电容器电介质区域中。 公开了其他实现。

公开(公告)号：US20130316153A1

公开(公告)日：2013-11-28

申请号：US13956211

申请日：2013-07-31

Applicant: Micron Technology, Inc.

Inventor： Nik Mirin ,  Tsai-Yu Huang ,  Vishwanath Bhat ,  Chris M. Carlson ,  Vassil N. Antonov

IPC: C01G23/04 ,  H05K1/02 ,  H01L23/373

CPC classification number: H01L21/02186 ,  C01G23/04 ,  C23C16/405 ,  C23C16/45534 ,  H01G4/085 ,  H01G4/1227 ,  H01G4/33 ,  H01L21/02233 ,  H01L21/02244 ,  H01L21/28556 ,  H01L21/32051 ,  H01L23/367 ,  H01L23/3735 ,  H01L23/3736 ,  H01L27/10808 ,  H01L27/1085 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/60 ,  H01L2924/0002 ,  H05K1/0203 ,  Y10T428/24802 ,  Y10T428/24975 ,  H01L2924/00

Abstract: Some embodiments include methods of forming rutile-type titanium oxide. A monolayer of titanium nitride may be formed. The monolayer of titanium nitride may then be oxidized at a temperature less than or equal to about 550° C. to convert it into a monolayer of rutile-type titanium oxide. Some embodiments include methods of forming capacitors that have rutile-type titanium oxide dielectric, and that have at least one electrode comprising titanium nitride. Some embodiments include thermally conductive stacks that contain titanium nitride and rutile-type titanium oxide, and some embodiments include methods of forming such stacks.

Abstract translation: 一些实施方案包括形成金红石型氧化钛的方法。 可以形成单层的氮化钛。 然后氮化钛单层可以在小于或等于约550℃的温度下被氧化，以将其转化为金红石型氧化钛的单层。 一些实施方案包括形成具有金红石型氧化钛电介质的电容器并且具有至少一个包含氮化钛的电极的方法。 一些实施方案包括含有氮化钛和金红石型氧化钛的导热叠层，并且一些实施方案包括形成这种叠层的方法。

公开(公告)号：US20240164114A1

公开(公告)日：2024-05-16

申请号：US18522637

申请日：2023-11-29

Applicant: Micron Technology, Inc.

Inventor： Hung-Wei Liu ,  Vassil N. Antonov ,  Ashonita A. Chavan ,  Darwin Franseda Fan ,  Jeffery B. Hull ,  Anish A. Khandekar ,  Masihhur R. Laskar ,  Albert Liao ,  Xue-Feng Lin ,  Manuj Nahar ,  Irina V. Vasilyeva

IPC: H10B53/20 ,  H01L21/223 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H10B51/20 ,  H10B51/30 ,  H10B53/30

CPC classification number: H10B53/20 ,  H01L21/223 ,  H01L29/1037 ,  H01L29/66666 ,  H01L29/7827 ,  H10B51/20 ,  H10B51/30 ,  H10B53/30

Abstract: A method of forming a vertical transistor comprising a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region comprises, in multiple time-spaced microwave annealing steps, microwave annealing at least the channel region. The multiple time-spaced microwave annealing steps reduce average concentration of elemental-form H in the channel region from what it was before start of the multiple time-spaced microwave annealing steps. The reduced average concentration of elemental-form H is 0.005 to less than 1 atomic percent. Structure embodiments are disclosed.

公开(公告)号：US11825662B2

公开(公告)日：2023-11-21

申请号：US17377665

申请日：2021-07-16

Applicant: Micron Technology, Inc.

Inventor： Clement Jacob ,  Vassil N. Antonov ,  Jaydeb Goswami ,  Albert Liao ,  Christopher W. Petz ,  Durai Vishak Nirmal Ramaswamy

IPC: H01L21/00 ,  H10B53/30 ,  H01L21/02 ,  H01L49/02

CPC classification number: H10B53/30 ,  H01L21/02175 ,  H01L21/02244 ,  H01L28/60

Abstract: A ferroelectric capacitor comprises two conductive capacitor electrodes having ferroelectric material there-between. At least one of the capacitor electrodes comprise MxSiOy, where “M” is at least one of Ru, Ti, Ta, Co, Pt, Ir, Os, Mo, V, W, Sr, Re, Rh, Pd, La, Zn, In, Sig, and Nb, Other aspects, including method, are disclosed.

公开(公告)号：US20210175239A1

公开(公告)日：2021-06-10

申请号：US16704657

申请日：2019-12-05

Applicant: Micron Technology, Inc.

Inventor： Clement Jacob ,  Vassil N. Antonov ,  Jaydeb Goswami ,  Albert Liao ,  Christopher W. Petz ,  Durai Vishak Nirmal Ramaswamy

IPC: H01L27/11507 ,  H01L49/02 ,  H01L21/02

Abstract: A ferroelectric capacitor comprises two conductive capacitor electrodes having ferroelectric material there-between. At least one of the capacitor electrodes comprise MxSiOy, where “M” is at least one of Ru, Ti, Ta, Co, Pt, Ir, Os, Mo, V, W, Sr, Re, Rh, Pd, La, Zn, In, Sn, and Nb. Other aspects, including method, are disclosed.