公开(公告)号：US20240321674A1

公开(公告)日：2024-09-26

申请号：US18510825

申请日：2023-11-16

Applicant: MEDIATEK INC.

Inventor： Pu-Shan HUANG ,  Chi-Yuan CHEN ,  Shih-Chin LIN

IPC: H01L23/367 ,  H01L23/00

CPC classification number: H01L23/3675 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/1611 ,  H01L2924/1632

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a semiconductor die, a lid, a liquid metal, a gel and a thermal dissipation structure. The semiconductor die is disposed on the substrate. The lid is disposed on the substrate and covers the semiconductor die. The lid has an opening to expose the semiconductor die. The liquid metal is disposed on the semiconductor die. The gel is disposed between the semiconductor die and the lid. The thermal dissipation structure is disposed on the lid and covers the opening. The semiconductor die, the gel and the thermal dissipation structure form a closed space for accommodating the liquid metal.

公开(公告)号：US20240087207A1

公开(公告)日：2024-03-14

申请号：US17944415

申请日：2022-09-14

Applicant: MediaTek Inc.

Inventor： Po-Yu HUANG ,  Shih-Chin LIN ,  Jen-Jung CHENG ,  Tu-Hsiu LEE

IPC: G06T15/00 ,  G06T1/20 ,  G06T7/50

CPC classification number: G06T15/005 ,  G06T1/20 ,  G06T7/50

Abstract: Disclosed herein are system, method, and computer program product embodiments for reducing GPU load by programmatically controlling shading rates in computer graphics. GPU load may be reduced by applying different shading rates to different screen regions. By reading the depth buffer of previous frames and performing image processing, thresholds may be calculated that control the shading rates. The approach may be run on any platform that supports VRS hardware and primitive- or image-based VRS. The approach may be applied on a graphics driver installed on a client device, in a firmware layer between hardware and a driver, in a software layer between a driver and an application, or in hardware on the client device. The approach is flexible and adaptable and calculates and sets the variable rate shading based on the graphics generated by an application without requiring the application developer to manually set variable rate shading.

公开(公告)号：US20160172292A1

公开(公告)日：2016-06-16

申请号：US14921015

申请日：2015-10-23

Applicant: MediaTek Inc.

Inventor： Wen-Sung HSU ,  Shih-Chin LIN

IPC: H01L23/498 ,  H01L23/31

CPC classification number: H01L23/3114 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The invention provides a semiconductor package assembly. The semiconductor package assembly includes a substrate structure having a cavity. A bottom surface of the cavity serves as a die-attach surface of the substrate structure. A semiconductor die is disposed in the cavity and mounted on the die-attach surface. A sidewall of the cavity is separated from the semiconductor die. An interposer is disposed on the substrate structure, covering the cavity.

Abstract translation: 本发明提供一种半导体封装组件。 半导体封装组件包括具有空腔的衬底结构。 腔的底表面用作衬底结构的管芯附着表面。 半导体管芯设置在空腔中并安装在管芯附着表面上。 空腔的侧壁与半导体管芯分离。 插入器设置在衬底结构上，覆盖空腔。

公开(公告)号：US20240274517A1

公开(公告)日：2024-08-15

申请号：US18418419

申请日：2024-01-22

Applicant: MEDIATEK INC.

Inventor： Fa-Chuan CHEN ,  Ta-Jen YU ,  Bo-Jiun YANG ,  Tsung-Yu PAN ,  Tai-Yu CHEN ,  Nai-Wei LIU ,  Shih-Chin LIN ,  Wen-Sung HSU

IPC: H01L23/498 ,  H01L21/28 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49816 ,  H01L21/28132 ,  H01L23/49822 ,  H01L24/05 ,  H01L24/13 ,  H01L25/0652 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/13025 ,  H01L2224/13147 ,  H01L2924/01029 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/351

Abstract: A semiconductor package structure includes a first component, a bonding structure on the first component, a second component connected to the first component, and a copper connector on the second component. The bonding structure includes a copper base on the first component and copper protruding portions on the copper base. The second component is connected to the first component by bonding the copper protruding portions to the copper connector, and the copper protruding portions are in contact with the copper connector.

公开(公告)号：US20200312732A1

公开(公告)日：2020-10-01

申请号：US16903458

申请日：2020-06-17

Applicant: MEDIATEK INC.

Inventor： Yen-Yao CHI ,  Nai-Wei LIU ,  Ta-Jen YU ,  Tzu-Hung LIN ,  Wen-Sung HSU ,  Shih-Chin LIN

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/00 ,  H01L21/56

Abstract: A semiconductor package structure includes a semiconductor die, a redistribution layer (RDL) structure, a protective insulating layer, and a conductive structure. The semiconductor die has a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. The RDL structure is on the first surface of the semiconductor die and is electrically coupled to the semiconductor die. The protective insulating layer covers the RDL structure, the second surface and the third surface of the semiconductor die. The conductive structure passes through the protective insulating layer and is electrically coupled to the RDL structure.

公开(公告)号：US20150115429A1

公开(公告)日：2015-04-30

申请号：US14585575

申请日：2014-12-30

Applicant: MediaTek Inc.

Inventor： Tai-Yu CHEN ,  Chung-Fa LEE ,  Wen-Sung HSU ,  Shih-Chin LIN

IPC: H01L23/373 ,  H01L23/00 ,  H01L23/367 ,  H01L23/498 ,  H01L23/29 ,  H01L23/31

CPC classification number: H01L23/3736 ,  H01L23/293 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/4334 ,  H01L23/49816 ,  H01L24/33 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package with reduced warpage problem is provided, including: a circuit board, having opposing first and second surfaces; a semiconductor chip, formed over a center portion of the first surface of the circuit board, having a first cross sectional dimension; a spacer, formed over a center portion of the semiconductor chip, having a second cross sectional dimension less than that of the first cross sectional dimension; an encapsulant layer, formed over the circuit board, covering the semiconductor chip and surrounding the spacer; a heat spreading layer, formed over the encapsulant layer and the spacer; and a plurality of solder balls, formed over the second surface of the circuit board, wherein a ratio between the first cross sectional dimension and the second cross sectional dimension is about 1:2-1:6.

Abstract translation: 提供一种具有降低翘曲问题的半导体封装，包括：具有相对的第一和第二表面的电路板; 半导体芯片，形成在电路板的第一表面的中心部分上，具有第一横截面尺寸; 形成在所述半导体芯片的中心部分上的间隔物，具有小于所述第一横截面尺寸的第二截面尺寸; 形成在电路板上的密封剂层，覆盖半导体芯片并围绕间隔物; 形成在密封剂层和间隔物上的散热层; 以及形成在电路板的第二表面上的多个焊球，其中第一横截面尺寸和第二横截面尺寸之间的比率为约1：2-1：6。

公开(公告)号：US20240386523A1

公开(公告)日：2024-11-21

申请号：US18630077

申请日：2024-04-09

Applicant: MEDIATEK INC.

Inventor： Po-Yu HUANG ,  Shih-Chin LIN ,  Ching-Yi TSAI ,  You-Ming TSAO

IPC: G06T1/20

Abstract: A computing system with graphics processor boosting is shown. The computing system has a graphics processing unit controlling a display, a code memory storing instructions, and a processor operating the graphics processing unit to control the display. The processor is configured to execute the instructions retrieved from the code memory to implement a plurality of graphics processor boosting modules for the graphics processing unit, and implement an activation controller that controls activation of the different graphics processor boosting modules through different configuration interfaces with balances between the different graphics processor boosting modules.

公开(公告)号：US20240297120A1

公开(公告)日：2024-09-05

申请号：US18407783

申请日：2024-01-09

Applicant: MEDIATEK INC.

Inventor： Wei-Yu CHEN ,  Yi-Lin TSAI ,  Nai-Wei LIU ,  Shih-Chin LIN ,  Wen-Sung HSU

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10 ,  H01L25/16

CPC classification number: H01L23/5381 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/19011 ,  H01L2924/19106

Abstract: A semiconductor package structure includes a first redistribution layer, a first semiconductor die, a second semiconductor die, a bridge structure, and a plurality of conductive bumps. The first semiconductor die and the second semiconductor die are disposed over the first redistribution layer. The bridge structure is disposed under the first redistribution layer. The first semiconductor die is electrically coupled to the second semiconductor die through the first redistribution layer and the bridge structure. The conductive bumps are disposed under the first redistribution layer and are coupled to the first redistribution layer. The bridge structure is disposed between at least two of the conductive bumps.

公开(公告)号：US20240145350A1

公开(公告)日：2024-05-02

申请号：US18475318

申请日：2023-09-27

Applicant: MEDIATEK Inc.

Inventor： Pu-Shan HUANG ,  Chi-Yuan CHEN ,  Shih-Chin LIN

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/16

CPC classification number: H01L23/4952 ,  H01L21/4885 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49513 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/16 ,  H01L2224/32225 ,  H01L2224/48155 ,  H01L2224/48225 ,  H01L2224/73265 ,  H01L2924/19101

Abstract: A semiconductor device is provided. The semiconductor device includes a carrier, an electronic component, an adapter, a first metal wire and a second metal wire. The electronic component is disposed on the carrier. The adapter is disposed on the carrier. The first metal wire connects the electronic component and the adapter. The second metal wire connects the adapter and the carrier.

公开(公告)号：US20160172334A1

公开(公告)日：2016-06-16

申请号：US14736684

申请日：2015-06-11

Applicant: MediaTek Inc.

Inventor： Wen-Sung HSU ,  Shih-Chin LIN ,  Andrew C. CHANG ,  Tao CHENG

IPC: H01L25/065 ,  H01L23/528 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/49827 ,  H01L23/528 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/12105 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311

Abstract: A chip package structure and a method for forming a chip package are provided. The chip package structure includes a first package which includes at least a semiconductor die, a dielectric structure surrounding the semiconductor die, and a plurality of conductive structures penetrating through the dielectric structure and surrounding the semiconductor die. The package structure also includes an interposer substrate over the first package and a plurality of conductive features in or over the interposer substrate. The package structure further includes a second package over the interposer substrate, and the first package electrically couples the second package through the conductive structures and the conductive features.

Abstract translation: 提供了芯片封装结构和芯片封装形成方法。 芯片封装结构包括第一封装，其包括至少半导体管芯，围绕半导体管芯的电介质结构，以及贯穿介电结构并围绕半导体管芯的多个导电结构。 所述封装结构还包括位于所述第一封装上的插入器衬底以及在所述插入器衬底中或之上的多个导电特征。 封装结构还包括在插入器基板上的第二封装，并且第一封装通过导电结构和导电特征将第二封装电耦合。