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    Memory system having an encoding processing circuit for redundant encoding process
    3.
    发明授权
    Memory system having an encoding processing circuit for redundant encoding process 有权
    具有用于冗余编码处理的编码处理电路的存储器系统

    公开(公告)号：US09105358B2

    公开(公告)日：2015-08-11

    申请号：US13157396

    申请日：2011-06-10

    Applicant: Masaya Tarui ,  Tatsunori Kanai ,  Yutaka Yamada

    Inventor： Masaya Tarui ,  Tatsunori Kanai ,  Yutaka Yamada

    IPC: G06F11/16 ,  G06F11/10 ,  G11C29/04 ,  G11C29/42 ,  G06F11/08 ,  H03M13/19

    CPC classification number: G06F11/1076 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0673 ,  G06F11/08 ,  G06F11/1012 ,  G06F11/1048 ,  G06F11/1666 ,  G11C29/42 ,  H03M13/19

    Abstract: In one embodiment, a memory system for writing redundant data output by an encoding processing circuit, comprises a memory, a encoding processing circuit, and a decoding circuit. The memory is electrically rewritable by using memory cells. The memory cells are capable of having two different resistance values corresponding to logical values of 1 or 0 respectively. The redundant data is read from and a predetermined logical value is written to the memory by flowing current in a same direction. The encoding processing circuit performs redundant encoding processing on target data and outputs redundant data. A number of bits having the predetermined logical value exceeds a number of bits having the logical value other than the predetermined logical value, for writing the redundant data to the memory. A decoding circuit reads data from the memory, and performs a decoding process on the data.

    Abstract translation: 在一个实施例中，用于写入由编码处理电路输出的冗余数据的存储器系统包括存储器，编码处理电路和解码电路。 存储器通过使用存储器单元进行电可重写。 存储单元能够分别具有对应于逻辑值1或0的两个不同的电阻值。 读取冗余数据，并且通过沿相同方向流动电流将预定的逻辑值写入存储器。 编码处理电路对目标数据进行冗余编码处理，并输出冗余数据。 具有预定逻辑值的位数超过具有除了预定逻辑值之外的逻辑值的比特数，用于将冗余数据写入存储器。 解码电路从存储器读取数据，并对数据进行解码处理。

    Memory device
    4.
    发明授权
    Memory device 有权
    内存设备

    公开(公告)号：US09075742B2

    公开(公告)日：2015-07-07

    申请号：US13360989

    申请日：2012-01-30

    Applicant: Masaya Tarui ,  Tatsunori Kanai ,  Yutaka Yamada ,  Hideki Yoshida

    Inventor： Masaya Tarui ,  Tatsunori Kanai ,  Yutaka Yamada ,  Hideki Yoshida

    IPC: G11C29/00 ,  G06F11/10 ,  G11C29/04

    CPC classification number: G06F11/1048 ,  G11C2029/0411

    Abstract: According to one embodiment, a memory device comprises a writing device that writes data bits, check bits for error corrections, and overhead bit(s) into a memory, each bit of the overhead bit(s) corresponding to each group of bit group(s) including at least one bit of the data bits and/or the check bits, each bit of the overhead bit(s) indicating whether the corresponding bit group has been inverted, a reading unit that reads the data bits, the check bits, and the overhead bit(s) from the memory, a correcting unit that corrects an error in the data bits and overhead bit(s) read from the memory, based on the check bits, and an inverting unit that inverts the data bits contained in the bit group corresponding to the overhead bit and outputs the inverted data bits as data read from the memory when the error-corrected overhead bit indicates that inversion has been performed.

    Abstract translation: 根据一个实施例，存储器件包括写数据位，用于纠错的校验位和开销位到存储器中的写入设备，每个比特组对应于每组比特组（ s）包括数据位和/或校验位的至少一位，开销位的每个位表示相应的位组是否已被反相，读取单元读取数据位，校验位， 以及来自存储器的开销位，校正单元，其基于校验位校正从存储器读取的数据位和开销位中的错误，以及反相单元，其将包含在存储器中的数据位反相 所述比特组对应于所述开销比特，并且当所述经纠错的开销比特指示已经执行了反转时，将所述反相的数据比特作为从所述存储器读取的数据输出。

    MEMORY DEVICE
    5.
    发明申请
    MEMORY DEVICE 有权
    内存设备

    公开(公告)号：US20120131418A1

    公开(公告)日：2012-05-24

    申请号：US13360989

    申请日：2012-01-30

    Applicant: Masaya Tarui ,  Tatsunori Kanai ,  Yutaka Yamada ,  Hideki Yoshida

    Inventor： Masaya Tarui ,  Tatsunori Kanai ,  Yutaka Yamada ,  Hideki Yoshida

    IPC: G11C29/52 ,  G06F11/10

    CPC classification number: G06F11/1048 ,  G11C2029/0411

    Abstract: According to one embodiment, a memory device comprises a writing device that writes data bits, check bits for error corrections, and overhead bit(s) into a memory, each bit of the overhead bit(s) corresponding to each group of bit group(s) including at least one bit of the data bits and/or the check bits, each bit of the overhead bit(s) indicating whether the corresponding bit group has been inverted, a reading unit that reads the data bits, the check bits, and the overhead bit(s) from the memory, a correcting unit that corrects an error in the data bits and overhead bit(s) read from the memory, based on the check bits, and an inverting unit that inverts the data bits contained in the bit group corresponding to the overhead bit and outputs the inverted data bits as data read from the memory when the error-corrected overhead bit indicates that inversion has been performed.

    Abstract translation: 根据一个实施例，存储器件包括写数据位，用于纠错的校验位和开销位到存储器中的写入设备，每个比特组对应于每组比特组（ s）包括数据位和/或校验位的至少一位，开销位的每个位表示相应的位组是否已被反相，读取单元读取数据位，校验位， 以及来自存储器的开销位，校正单元，其基于校验位校正从存储器读取的数据位和开销位中的错误，以及反相单元，其将包含在存储器中的数据位反相 所述比特组对应于所述开销比特，并且当所述经纠错的开销比特指示已经执行了反转时，将所述反相的数据比特作为从所述存储器读取的数据输出。

    COMPUTER SYSTEM AND COMPUTER SYSTEM CONTROL METHOD
    6.
    发明申请
    COMPUTER SYSTEM AND COMPUTER SYSTEM CONTROL METHOD 有权
    计算机系统和计算机系统控制方法

    公开(公告)号：US20120117407A1

    公开(公告)日：2012-05-10

    申请号：US13310892

    申请日：2011-12-05

    Applicant: Tatsunori Kanai ,  Yutaka Yamada ,  Hideki Yoshida ,  Masaya Tarui

    Inventor： Tatsunori Kanai ,  Yutaka Yamada ,  Hideki Yoshida ,  Masaya Tarui

    IPC: G06F1/32

    CPC classification number: G06F1/3275 ,  Y02D10/13 ,  Y02D10/14

    Abstract: According to one embodiment, a computer system comprises a first memory that stores a first program, a second memory that stores a second program or data, a processor, a first and a second power control circuits. The first power control circuit causes the first memory to operate at a first power consumption when detecting change of an input signal to the processor, and causes the first memory to operate at a second power consumption smaller than the first power consumption and transmits a temporary halt instruction to the processor when the execution of the first program or the second program by the processor is completed. The second power control circuit causes the second memory to operate at a third power consumption before the processor executes the second program, reads or writes the data.The second memory accepts read and write operations while operating at the third power consumption.

    Abstract translation: 根据一个实施例，计算机系统包括存储第一程序的第一存储器，存储第二程序或数据的第二存储器，处理器，第一和第二功率控制电路。 当检测到对处理器的输入信号的变化时，第一功率控制电路使得第一存储器以第一功率消耗操作，并且使得第一存储器以比第一功耗小的第二功耗工作，并且发送暂时停止 当处理器执行第一程序或第二程序完成时，指令到处理器。 第二功率控制电路使得第二存储器在处理器执行第二程序之前以第三功耗操作，读取或写入数据。 第二个存储器在以第三次功耗运行的同时接受读写操作。

    RANDOM NUMBER GENERATOR
    8.
    发明申请
    RANDOM NUMBER GENERATOR 失效
    随机数发电机

    公开(公告)号：US20120026784A1

    公开(公告)日：2012-02-02

    申请号：US13205737

    申请日：2011-08-09

    Applicant: Tatsunori Kanai ,  Masaya Tarui ,  Yutaka Yamada

    Inventor： Tatsunori Kanai ,  Masaya Tarui ,  Yutaka Yamada

    IPC: G11C11/00

    CPC classification number: G06F7/588 ,  H04L9/0866

    Abstract: According to an aspect of embodiments, there is provided a random number generating circuit including at least one magnetic tunnel junction (MTJ) element and a control circuit. The MTJ element comes into a high resistance state corresponding to a first logical value and also comes into a low resistance state corresponding to a second logical value different from the first logical value. The control circuit supplies the MTJ element with a first current for stochastically reversing the MTJ element from the high resistance state to the low resistance state when the MTJ element is in the high resistance state, and supplies the MTJ element with a second current for stochastically reversing the MTJ element from the low resistance state to the high resistance state when the MTJ element is in the low resistance state.

    Abstract translation: 根据实施例的一个方面，提供一种包括至少一个磁隧道结（MTJ）元件和控制电路的随机数产生电路。 MTJ元件对应于第一逻辑值进入高电阻状态，并且也进入与不同于第一逻辑值的第二逻辑值相对应的低电阻状态。 当MTJ元件处于高电阻状态时，控制电路向MTJ元件提供第一电流，用于将MTJ元件从高电阻状态随机反向到低电阻状态，并且向MTJ元件提供用于随机反转的第二电流 当MTJ元件处于低电阻状态时，MTJ元件从低电阻状态到高电阻状态。

    Storage apparatus including non-volatile SRAM
    9.
    发明授权
    Storage apparatus including non-volatile SRAM 有权
    存储设备包括非易失性SRAM

    公开(公告)号：US07903451B2

    公开(公告)日：2011-03-08

    申请号：US12404510

    申请日：2009-03-16

    Applicant: Yutaka Yamada ,  Tatsunori Kanai ,  Masaya Tarui ,  Keiko Abe

    Inventor： Yutaka Yamada ,  Tatsunori Kanai ,  Masaya Tarui ,  Keiko Abe

    IPC: G11C11/00

    CPC classification number: G11C13/00 ,  G11C11/1659 ,  G11C11/56 ,  G11C11/5607 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0069 ,  G11C14/0081 ,  G11C2013/0073

    Abstract: According to one embodiment, a storage apparatus includes: a first inverter; a second inverter; a first storage element having a first state and a second state; and a second storage element having a third state and a fourth state, wherein the first storage element is brought into the first state when a current flows from the first storage element to the first storage element and is brought into the second state when the current flows from the first storage element to the first storage element, wherein the second storage element is brought into the fourth state when a current flows from the second storage element to the second storage element and is brought into the third state when the current flows from the second storage element to the second storage element.

    Abstract translation: 根据一个实施例，一种存储装置包括：第一反相器; 第二个逆变器; 具有第一状态和第二状态的第一存储元件; 以及具有第三状态和第四状态的第二存储元件，其中当电流从第一存储元件流向第一存储元件时，第一存储元件处于第一状态，并且当电流流动时处于第二状态 从第一存储元件到第一存储元件，其中当电流从第二存储元件流到第二存储元件时，第二存储元件处于第四状态，并且当电流从第二存储元件 存储元件到第二存储元件。

    Switching a processor and memory to a power saving mode when waiting to access a second slower non-volatile memory on-demand
    10.
    发明授权
    Switching a processor and memory to a power saving mode when waiting to access a second slower non-volatile memory on-demand 有权
    当等待按需访问第二个较慢的非易失性存储器时，将处理器和存储器切换到省电模式

    公开(公告)号：US08683249B2

    公开(公告)日：2014-03-25

    申请号：US13310892

    申请日：2011-12-05

    Applicant: Tatsunori Kanai ,  Yutaka Yamada ,  Hideki Yoshida ,  Masaya Tarui

    Inventor： Tatsunori Kanai ,  Yutaka Yamada ,  Hideki Yoshida ,  Masaya Tarui

    IPC: G06F1/26

    CPC classification number: G06F1/3275 ,  Y02D10/13 ,  Y02D10/14

    Abstract: According to one embodiment, a computer system comprises a first memory that stores a first program, a second memory that stores a second program or data, a processor, a first and a second power control circuits. The first power control circuit causes the first memory to operate at a first power consumption when detecting change of an input signal to the processor, and causes the first memory to operate at a second power consumption smaller than the first power consumption and transmits a temporary halt instruction to the processor when the execution of the first program or the second program by the processor is completed. The second power control circuit causes the second memory to operate at a third power consumption before the processor executes the second program, reads or writes the data. The second memory accepts read and write operations while operating at the third power consumption.

    Abstract translation: 根据一个实施例，计算机系统包括存储第一程序的第一存储器，存储第二程序或数据的第二存储器，处理器，第一和第二功率控制电路。 当检测到对处理器的输入信号的变化时，第一功率控制电路使得第一存储器以第一功率消耗操作，并且使得第一存储器以比第一功耗小的第二功耗工作，并且发送暂时停止 当处理器执行第一程序或第二程序完成时，指令到处理器。 第二功率控制电路使得第二存储器在处理器执行第二程序之前以第三功耗操作，读取或写入数据。 第二个存储器在以第三次功耗运行的同时接受读写操作。

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