公开(公告)号：US20130181184A1

公开(公告)日：2013-07-18

申请号：US13547567

申请日：2012-07-12

Applicant: Kiwamu SAKUMA ,  Masahiro KIYOTOSHI ,  Atsuhiro KINOSHITA ,  Haruka KUSAI

Inventor： Kiwamu SAKUMA ,  Masahiro KIYOTOSHI ,  Atsuhiro KINOSHITA ,  Haruka KUSAI

IPC: H01L27/24 ,  H01L21/8234

CPC classification number: H01L45/1233 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/1211 ,  H01L27/222 ,  H01L27/2454 ,  H01L27/2481 ,  H01L29/7881 ,  H01L29/792 ,  H01L45/1206 ,  H01L45/1253

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes fin-type stacked layer structures. Each of the structures includes semiconductor layers stacked in a perpendicular direction. Assist gate electrodes are disposed in an in-plane direction and divided on a surface in the perpendicular direction of the structures.

公开(公告)号：US20080182381A1

公开(公告)日：2008-07-31

申请号：US11874292

申请日：2007-10-18

Applicant: Masahiro KIYOTOSHI

Inventor： Masahiro KIYOTOSHI

IPC: H01L21/76

CPC classification number: H01L21/76229

Abstract: A first trench and a second trench having width wider than the first trench are simultaneously formed in a main surface area of a semiconductor substrate. The width of an opening portion of the first trench is made narrower by forming a first insulating film on the main surface of the semiconductor substrate and in the first and second trenches. A second insulating film is formed on the first insulating film by use of a high-density plasma-CVD method to form a void in the first trench while covering the opening portion of the first trench, and the second trench is filled with the second insulating film. Then, part of the second insulating film which covers the opening portion is removed by anisotropic etching and the void is filled with an insulating film having fluidity at the film formation time.

Abstract translation: 在半导体衬底的主表面区域中同时形成宽度大于第一沟槽的第一沟槽和第二沟槽。 通过在半导体衬底的主表面上和第一沟槽和第二沟槽中形成第一绝缘膜，使第一沟槽的开口部分的宽度变窄。 通过使用高密度等离子体CVD法在第一绝缘膜上形成第二绝缘膜，以在覆盖第一沟槽的开口部分的同时在第一沟槽中形成空隙，并且第二沟槽填充有第二绝缘膜 电影。 然后，通过各向异性蚀刻去除覆盖开口部分的第二绝缘膜的一部分，并且在成膜时间填充具有流动性的绝缘膜。

公开(公告)号：US20120068144A1

公开(公告)日：2012-03-22

申请号：US13097375

申请日：2011-04-29

Applicant: Ryota FUJITSUKA ,  Masahiro KIYOTOSHI ,  Katsuyuki SEKINE ,  Mitsuru SATO

Inventor： Ryota FUJITSUKA ,  Masahiro KIYOTOSHI ,  Katsuyuki SEKINE ,  Mitsuru SATO

IPC: H01L45/00

CPC classification number: H01L45/146 ,  G11C11/5685 ,  G11C13/0007 ,  G11C2213/72 ,  H01L45/1233

Abstract: According to one embodiment, there are provided a first electrode, a second electrode, first and second variable-resistance layers that are arranged between the first electrode and the second electrode, and at least one non variable-resistance layer that is arranged so that positions of the first and second variable-resistance layers between the first electrode and the second electrode are symmetrical to each other.

Abstract translation: 根据一个实施例，提供了布置在第一电极和第二电极之间的第一电极，第二电极，第一和第二可变电阻层，以及至少一个非可变电阻层，其被布置成使得位置 在第一电极和第二电极之间的第一和第二可变电阻层彼此对称。

公开(公告)号：US20090194810A1

公开(公告)日：2009-08-06

申请号：US12361340

申请日：2009-01-28

Applicant: Masahiro KIYOTOSHI ,  Hiroshi Kubota

Inventor： Masahiro KIYOTOSHI ,  Hiroshi Kubota

IPC: H01L29/792 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L27/11575 ,  H01L21/76229 ,  H01L21/84 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11573 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/42336

Abstract: A stacked film including a gate dielectric film and electrode film of each memory cell of a flash memory is formed on a semiconductor substrate. The stacked film is patterned by reactive ion etching to form an isolation trench for formation of an element isolation region and the surface of the semiconductor substrate is exposed to the internal portion of the isolation trench. An O3-TEOS film exhibiting underlying material selectivity during the deposition is formed in the isolation trench as the first filling dielectric film and then the isolation trench is filled with the second filling dielectric film to form an element isolation region of an STI structure.

Abstract translation: 在半导体衬底上形成包括闪存的每个存储单元的栅介质膜和电极膜的叠层膜。 通过反应离子蚀刻对层叠的膜进行构图以形成用于形成元件隔离区域的隔离沟槽，并且半导体衬底的表面暴露于隔离沟槽的内部部分。 在作为第一填充介电膜的隔离沟槽中形成了在沉积期间显示出潜在材料选择性的O3-TEOS膜，然后用第二填充介电膜填充隔离沟槽，以形成STI结构的元件隔离区域。

公开(公告)号：US20090072323A1

公开(公告)日：2009-03-19

申请号：US12209116

申请日：2008-09-11

Applicant: Masahiro KIYOTOSHI

Inventor： Masahiro KIYOTOSHI

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L21/76229 ,  H01L21/823481 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11543 ,  H01L27/11573

Abstract: In a nonvolatile semiconductor memory device which has a nonvolatile memory cell portion, a low-voltage operating circuit portion of a peripheral circuit region and a high-voltage operating circuit portion of the peripheral circuit region formed on a substrate and in which elements of the above portions are isolated from one another by filling insulating films, the upper surface of the filling insulating films in the high-voltage operating circuit portion lies above the surface of the substrate and the upper surface of at least part of the filling insulating films in the low-voltage operating circuit portion is pulled back to a portion lower than the surface of the substrate.

Abstract translation: 在具有非易失性存储单元部分的非易失性半导体存储器件中，外围电路区域的低电压工作电路部分和形成在衬底上的外围电路区域的高电压工作电路部分，并且上述元件 部分通过填充绝缘膜彼此隔离，高压操作电路部分中的填充绝缘膜的上表面位于基板的表面上方，并且至少部分填充绝缘膜的上表面在低 电压操作电路部分被拉回到比基板的表面低的部分。

公开(公告)号：US20080169499A1

公开(公告)日：2008-07-17

申请号：US12014869

申请日：2008-01-16

Applicant: Masahiro KIYOTOSHI

Inventor： Masahiro KIYOTOSHI

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L27/105 ,  H01L27/11526 ,  H01L27/11543 ,  H01L29/42336 ,  H01L29/7881

Abstract: A flash memory includes a memory cell portion and peripheral circuit portion. The memory cell portion has first gate dielectric films formed on the main surface of a semiconductor substrate and floating gate electrode layers formed on the first gate dielectric films. The peripheral circuit portion has second gate dielectric films formed on the main surface of the semiconductor substrate and gate electrode layers formed on the second gate dielectric films. The penetration depth of a bird's beak formed in contact with the upper and bottom surfaces of the second gate dielectric film is larger than the penetration depth of a bird's beak formed in contact with the upper and bottom surfaces of the first gate dielectric film.

Abstract translation: 闪速存储器包括存储单元部分和外围电路部分。 存储单元部分具有形成在半导体衬底的主表面上的第一栅极电介质膜和形成在第一栅极电介质膜上的浮动栅极电极层。 外围电路部分具有形成在半导体衬底的主表面上的第二栅极电介质膜和形成在第二栅极电介质膜上的栅极电极层。 与第二栅极电介质膜的上表面和底表面接触形成的鸟嘴的穿透深度大于与第一栅极介电膜的上表面和底表面接触形成的鸟嘴的穿透深度。

公开(公告)号：US20130134372A1

公开(公告)日：2013-05-30

申请号：US13689026

申请日：2012-11-29

Applicant: Kiwamu SAKUMA ,  Haruka KUSAI ,  Shosuke FUJII ,  Li ZHANG ,  Masahiro KIYOTOSHI ,  Masao SHINGU

Inventor： Kiwamu SAKUMA ,  Haruka KUSAI ,  Shosuke FUJII ,  Li ZHANG ,  Masahiro KIYOTOSHI ,  Masao SHINGU

IPC: H01L45/00 ,  H01L21/265

CPC classification number: H01L27/1157 ,  H01L21/265 ,  H01L21/845 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/1211 ,  H01L27/2436 ,  H01L27/2481 ,  H01L29/42332 ,  H01L29/7881 ,  H01L29/792 ,  H01L45/04

Abstract: According to one embodiment, a semiconductor device includes first to n-th semiconductor layers (n is a natural number equal to or more than 2) being stacked in order from a surface of an insulating layer in a first direction perpendicular to the surface of the insulating layer, the first to n-th semiconductor layers extending in a second direction parallel to the surface of the insulating layer, the first to n-th semiconductor layers being insulated from each other, a common electrode connected to the first to n-th semiconductor layers in a first end of the second direction thereof, and a layer select transistor which uses the first to n-th semiconductor layers as channels and which selects one of the first to n-th semiconductor layers.

Abstract translation: 根据一个实施例，半导体器件包括第一至第n半导体层（n为等于或大于2的自然数），从绝缘层的表面依次堆叠在与第 绝缘层，所述第一至第n半导体层在与所述绝缘层的表面平行的第二方向上延伸，所述第一至第n半导体层彼此绝缘，公共电极连接到所述第一至第n 半导体层，其第二方向的第一端，以及使用第一至第n半导体层作为沟道并选择第一至第n半导体层之一的层选择晶体管。

公开(公告)号：US20090294836A1

公开(公告)日：2009-12-03

申请号：US12476799

申请日：2009-06-02

Applicant: Masahiro KIYOTOSHI

Inventor： Masahiro KIYOTOSHI

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L27/11582 ,  H01L27/11573 ,  H01L27/11578

Abstract: A nonvolatile semiconductor storage device includes: a plurality of stacked units juxtaposed on a major surface of a substrate, each stacked unit aligning in a first direction parallel to the major surface of the substrate; and a gate electrode aligning parallel to the major surface in a second direction non-parallel to the first direction. Each of the plurality of stacked units includes a plurality of stacked semiconductor layers via an insulating layer. The plurality of stacked units are juxtaposed so that the spacings between adjacent stacked units are alternately a first spacing and a second spacing larger than the first spacing. The second spacing is provided at a periodic interval four times a size of a half pitch F of the bit line. The gate electrode includes a protruding portion that enters into a gap of the second spacing between the stacked units. A first insulating film, a charge storage layer, and a second insulating film are provided between a side face of the semiconductor layer and the protruding portion.

Abstract translation: 非易失性半导体存储装置包括：多个叠置的单元并置在基板的主表面上，每个堆叠单元在平行于基板的主表面的第一方向上对准; 以及在与第一方向不平行的第二方向上平行于主表面对准的栅电极。 多个堆叠单元中的每一个经由绝缘层包括多个层叠的半导体层。 多个堆叠单元并置，使得相邻层叠单元之间的间隔交替地为第一间隔，而第二间隔大于第一间隔。 第二间隔以比特线的半间距F的大小的四倍的周期性间隔提供。 栅电极包括进入堆叠单元之间的第二间隔的间隙的突出部分。 第一绝缘膜，电荷存储层和第二绝缘膜设置在半导体层的侧面和突出部之间。

公开(公告)号：US20120280303A1

公开(公告)日：2012-11-08

申请号：US13366845

申请日：2012-02-06

Applicant: Masahiro KIYOTOSHI ,  Kiwamu Sakuma ,  Haruka Kusai

Inventor： Masahiro KIYOTOSHI ,  Kiwamu Sakuma ,  Haruka Kusai

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L27/11556 ,  H01L27/11524 ,  H01L29/7889

Abstract: According to one embodiment, a first trench extending in a first direction is formed in a stacked structure in which a plurality of spacer films and a plurality of channel semiconductor films are alternately stacked. A first space is formed by forming a recess in the channel semiconductor films from the first trench. A tunnel dielectric film is formed in the first space, and the first space is further filled with a floating gate electrode film. Second trenches that divide the stacked structure at predetermined interval in the first direction are formed so as to divide the floating gate electrode film between memory cells adjacent to each other in the first direction but not to divide the channel semiconductor films.

Abstract translation: 根据一个实施例，沿着第一方向延伸的第一沟槽以堆叠结构形成，其中多个隔离膜和多个沟道半导体膜交替堆叠。 通过在沟道半导体膜中形成来自第一沟槽的凹部来形成第一空间。 在第一空间中形成隧道电介质膜，并且第一空间进一步填充浮栅电极膜。 形成在第一方向上以预定间隔划分堆叠结构的第二沟槽，以便在第一方向上彼此相邻的存储单元之间划分浮栅电极膜，但不划分沟道半导体膜。

公开(公告)号：US20120060752A1

公开(公告)日：2012-03-15

申请号：US13049456

申请日：2011-03-16

Applicant: Masahiro KIYOTOSHI ,  Shigeki Sugimoto

Inventor： Masahiro KIYOTOSHI ,  Shigeki Sugimoto

IPC: B05C9/12 ,  B05C9/02 ,  B05C11/00 ,  B05C13/00 ,  B05C11/02

CPC classification number: H01L21/67109 ,  H01L21/67742 ,  H01L21/68707

Abstract: An apparatus for forming silicon oxide film is disclosed. The apparatus includes a spin coating unit, a carrying unit, and an oxidation unit. The spin coating unit forms a polymer film above a substrate by spin coating a solution including a polymer containing a silazane bond dissolved in an organic solvent. The carrying unit carries the substrate to the oxidation unit without contacting the polymer film. The oxidation unit, when receiving the substrate from the carrying unit, converts the polymer film into the silicon oxide film by either immersing the polymer film with a heated aqueous solution containing hydrogen peroxide, spraying the heated aqueous solution containing hydrogen peroxide over the polymer film, or exposing the polymer film to a reaction gas containing a hydrogen peroxide vapor. The apparatus, by itself, completes the polymer film formation and the polymer-to-silicon oxide film conversion within the apparatus itself.

Abstract translation: 公开了一种用于形成氧化硅膜的设备。 该设备包括旋涂单元，承载单元和氧化单元。 旋涂单元通过旋涂包含溶解在有机溶剂中的含有硅氮烷键的聚合物的溶液在基底上形成聚合物膜。 承载单元将基板运送到氧化单元而不与聚合物膜接触。 氧化单元在从承载单元接收基板时，通过将聚合物膜浸入含有过氧化氢的加热水溶液中，将聚合物膜转化为氧化硅膜，将加热的含有过氧化氢的水溶液喷洒在聚合物膜上， 或将聚合物膜暴露于含有过氧化氢蒸气的反应气体中。 该装置本身完成了聚合物膜的形成和在设备本身内的聚合物 - 氧化硅膜的转换。