公开(公告)号：US20070290249A1

公开(公告)日：2007-12-20

申请号：US11844853

申请日：2007-08-24

Applicant: Martin Popp ,  Frank Jakubowski ,  Juergen Holz ,  Lars Heineck

Inventor： Martin Popp ,  Frank Jakubowski ,  Juergen Holz ,  Lars Heineck

IPC: H01L29/94

CPC classification number: H01L29/945 ,  H01L21/26586 ,  H01L27/0207 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/10873 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10894

Abstract: An integrated circuit includes a memory cell array comprising memory cells with a transistor. The transistors are formed in active areas. The memory cell array further includes bit lines oriented in a first direction and word lines oriented in a second direction. The active areas extend in the second direction. The bottom side of each gate electrode of the transistors is disposed under the bottom side of each word line. In addition, the word lines are disposed over the bit lines.

Abstract translation: 集成电路包括具有晶体管的存储单元的存储单元阵列。 晶体管形成在有源区域中。 存储单元阵列还包括沿第一方向定向的位线和朝向第二方向的字线。 有源区域沿第二方向延伸。 晶体管的每个栅电极的底侧设置在每个字线的底侧的下方。 此外，字线设置在位线之上。

公开(公告)号：US07274060B2

公开(公告)日：2007-09-25

申请号：US11152793

申请日：2005-06-15

Applicant: Martin Popp ,  Frank Jakubowski ,  Juergen Holz ,  Lars Heineck

Inventor： Martin Popp ,  Frank Jakubowski ,  Juergen Holz ,  Lars Heineck

IPC: H01L21/8244 ,  H01L29/94

CPC classification number: H01L29/945 ,  H01L21/26586 ,  H01L27/0207 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/10873 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10894

Abstract: A memory cell array includes memory cells with storage capacitor and an access transistor. The access transistors are formed in active areas. The memory cell array further includes bit lines oriented in a first direction and word lines oriented in a second direction. The active areas extend in the second direction. The bottom side of each gate electrode of the transistors is disposed beneath the bottom side of each word line. In addition, the word lines are disposed above the bit lines.

Abstract translation: 存储单元阵列包括具有存储电容器和存取晶体管的存储单元。 存取晶体管形成在有源区域中。 存储单元阵列还包括沿第一方向定向的位线和朝向第二方向的字线。 有源区域沿第二方向延伸。 晶体管的每个栅电极的底侧设置在每个字线的底侧的下方。 此外，字线设置在位线上方。

公开(公告)号：US20060284225A1

公开(公告)日：2006-12-21

申请号：US11152793

申请日：2005-06-15

Applicant: Martin Popp ,  Frank Jakubowski ,  Juergen Holz ,  Lars Heineck

Inventor： Martin Popp ,  Frank Jakubowski ,  Juergen Holz ,  Lars Heineck

IPC: H01L21/8244 ,  H01L29/94

CPC classification number: H01L29/945 ,  H01L21/26586 ,  H01L27/0207 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/10873 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10894

Abstract: A memory cell array includes memory cells with storage capacitor and an access transistor. The access transistors are formed in active areas. The memory cell array further includes bit lines oriented in a first direction and word lines oriented in a second direction. The active areas extend in the second direction. The bottom side of each gate electrode of the transistors is disposed beneath the bottom side of each word line. In addition, the word lines are disposed above the bit lines.

Abstract translation: 存储单元阵列包括具有存储电容器和存取晶体管的存储单元。 存取晶体管形成在有源区域中。 存储单元阵列还包括沿第一方向定向的位线和朝向第二方向的字线。 有源区域沿第二方向延伸。 晶体管的每个栅电极的底侧设置在每个字线的底侧的下方。 此外，字线设置在位线上方。

公开(公告)号：US07875977B2

公开(公告)日：2011-01-25

申请号：US12243008

申请日：2008-10-01

Applicant: Hans-Joachim Barth ,  Juergen Holz

Inventor： Hans-Joachim Barth ,  Juergen Holz

IPC: H01L23/48

CPC classification number: H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76873 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L2221/1089 ,  H01L2924/0002 ,  Y10T428/24479 ,  H01L2924/00

Abstract: Barrier layers for conductive features and methods of formation thereof are disclosed. A first barrier material is deposited on top surfaces of an insulating material, and a second barrier material is deposited on sidewalls of the insulating material, wherein the second barrier material is different than the first barrier material. The first barrier material induces grain growth of a subsequently deposited conductive material at a first rate, and the second barrier material induces grain growth of the conductive material at a second rate, wherein the second rate is slower than the first rate.

Abstract translation: 公开了用于导电特征的阻挡层及其形成方法。 第一阻挡材料沉积在绝缘材料的顶表面上，并且第二阻挡材料沉积在绝缘材料的侧壁上，其中第二阻挡材料不同于第一阻挡材料。 第一阻挡材料以第一速率诱导随后沉积的导电材料的晶粒生长，并且第二阻挡材料以第二速率诱导导电材料的晶粒生长，其中第二速率比第一速率慢。

公开(公告)号：US07824993B2

公开(公告)日：2010-11-02

申请号：US12431214

申请日：2009-04-28

Applicant: Juergen Holz ,  Klaus Schruefer ,  Helmut Tews

Inventor： Juergen Holz ,  Klaus Schruefer ,  Helmut Tews

IPC: H01L21/336

CPC classification number: H01L29/66636 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/3205 ,  H01L29/0653 ,  H01L29/41783

Abstract: A method for fabricating a field-effect transistor with local source/drain insulation. The method includes forming and patterning a gate stack with a gate layer and a gate dielectric on a semiconductor substrate; forming source and drain depressions at the gate stack in the semiconductor substrate; forming a depression insulation layer at least in a bottom region of the source and drain depressions; and filling the at least partially insulated source and drain depressions with a filling layer for realizing source and drain regions. Further, the step of forming source and drain depressions at the gate stack in the semiconductor substrate includes that first depressions are formed for realizing channel connection regions in the semiconductor substrate, spacers are formed at the gate stack, and second depressions are formed using the spacers as a mask in the first depressions and in the semiconductor substrate.

Abstract translation: 一种制造具有局部源极/漏极绝缘的场效应晶体管的方法。 该方法包括在半导体衬底上形成和图案化具有栅极层和栅极电介质的栅叠层; 在半导体衬底中的栅极堆叠处形成源极和漏极凹陷; 至少在所述源极和漏极凹陷的底部区域中形成凹陷绝缘层; 以及用用于实现源极和漏极区域的填充层填充所述至少部分绝缘的源极和漏极凹部。 此外，在半导体衬底中的栅极堆叠处形成源极和漏极凹陷的步骤包括形成用于实现半导体衬底中的沟道连接区域的第一凹陷，在栅极堆叠处形成间隔物，并且使用间隔件形成第二凹陷 作为第一凹部和半导体衬底中的掩模。

公开(公告)号：US20080283910A1

公开(公告)日：2008-11-20

申请号：US11748864

申请日：2007-05-15

Applicant: Lars Dreeskornfeld ,  Dongping Wu ,  Jessica Hartwich ,  Juergen Holz ,  Arnd Scholz

Inventor： Lars Dreeskornfeld ,  Dongping Wu ,  Jessica Hartwich ,  Juergen Holz ,  Arnd Scholz

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/823456 ,  H01L21/823431 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785

Abstract: An integrated circuit and method of forming an integrated circuit is disclosed. One embodiment includes a FinFET of a first type having a first gate electrode and a FinFET of a second type having a second gate electrode. The first gate electrode is formed in a gate groove that is defined in a semiconductor substrate and a bottom side of a portion of the second gate electrode is disposed above a main surface of the semiconductor substrate.

Abstract translation: 公开了一种形成集成电路的集成电路和方法。 一个实施例包括具有第一栅极和第二类型的具有第二栅电极的FinFET的第一类型的FinFET。 第一栅电极形成在限定在半导体衬底中的栅极沟槽中，并且第二栅电极的一部分的底侧设置在半导体衬底的主表面上方。

公开(公告)号：US09240462B2

公开(公告)日：2016-01-19

申请号：US12888938

申请日：2010-09-23

Applicant: Juergen Holz ,  Klaus Schruefer ,  Helmut Tews

Inventor： Juergen Holz ,  Klaus Schruefer ,  Helmut Tews

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/66636 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/3205 ,  H01L29/0653 ,  H01L29/41783

Abstract: A method for fabricating a field-effect transistor with local source/drain insulation. The method includes forming and patterning a gate stack with a gate layer and a gate dielectric on a semiconductor substrate; forming source and drain depressions at the gate stack in the semiconductor substrate; forming a depression insulation layer at least in a bottom region of the source and drain depressions; and filling the at least partially insulated source and drain depressions with a filling layer for realizing source and drain regions.

Abstract translation: 一种制造具有局部源极/漏极绝缘的场效应晶体管的方法。 该方法包括在半导体衬底上形成和图案化具有栅极层和栅极电介质的栅叠层; 在半导体衬底中的栅极堆叠处形成源极和漏极凹陷; 至少在所述源极和漏极凹陷的底部区域中形成凹陷绝缘层; 以及用用于实现源极和漏极区域的填充层填充所述至少部分绝缘的源极和漏极凹部。

公开(公告)号：US20090269914A1

公开(公告)日：2009-10-29

申请号：US12497949

申请日：2009-07-06

Applicant: Alexander Gschwandtner ,  Juergen Holz ,  Michael Schrenk

Inventor： Alexander Gschwandtner ,  Juergen Holz ,  Michael Schrenk

IPC: H01L21/46

CPC classification number: H01L21/02274 ,  C23C16/345 ,  C23C16/45523 ,  C23C16/45542 ,  C23C16/511 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02211 ,  H01L21/02258 ,  H01L21/0228 ,  H01L21/318 ,  H01L21/3185 ,  H01L21/76807 ,  H01L23/5223 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Process for forming a dielectric. The process may include forming the dielectric on a metallization and capacitor arrangement. The process allows the direct application of a dielectric layer to a copper-containing metallization. Accordingly, two process gases may be excited with different plasma powers per unit substrate area, or one process gas may be excited with a plasma and another process gas may not be excited.

Abstract translation: 电介质形成工艺。 该方法可以包括在金属化和电容器布置上形成电介质。 该方法允许将电介质层直接施加到含铜金属化。 因此，可以用每单位衬底面积的不同等离子体功率激发两种处理气体，或者一种工艺气体可以用等离子体激发，另一种工艺气体可能不被激发。

公开(公告)号：US20090101975A1

公开(公告)日：2009-04-23

申请号：US11816822

申请日：2005-12-09

Applicant: Juergen Holz ,  Ronald Kakoschke ,  Thomas Nirschl ,  Christian Pacha ,  Klaus Schruefer ,  Thomas Schulz ,  Doris Schmitt-Landsiedel

Inventor： Juergen Holz ,  Ronald Kakoschke ,  Thomas Nirschl ,  Christian Pacha ,  Klaus Schruefer ,  Thomas Schulz ,  Doris Schmitt-Landsiedel

IPC: H01L29/02

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/1052 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/7391 ,  H01L29/7392 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7854 ,  H01L29/7856

Abstract: An explanation is given of, inter alia, tunnel field effect transistors having a thicker gate dielectric (GD1) in comparison with other transistors (T2) on the same integrated circuit arrangement (10). As an alternative or in addition, said tunnel field effect transistors have gate regions at mutually remote sides of a channel forming region or an interface between the connection regions (D1, S1) of the tunnel field effect transistor.

Abstract translation: 具体地说，具有与同一集成电路装置（10）上的其它晶体管（T2）相比具有较厚栅极电介质（GD1）的隧道场效应晶体管的解释。 作为替代或另外，所述隧道场效应晶体管具有在沟道形成区域的相对远侧的栅极区域或隧道场效应晶体管的连接区域（D1，S1）之间的界面。

公开(公告)号：US20060202345A1

公开(公告)日：2006-09-14

申请号：US11079738

申请日：2005-03-14

Applicant: Hans-Joachim Barth ,  Juergen Holz

Inventor： Hans-Joachim Barth ,  Juergen Holz

IPC: H01L23/48

CPC classification number: H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76873 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L2221/1089 ,  H01L2924/0002 ,  Y10T428/24479 ,  H01L2924/00

Abstract: Barrier layers for conductive features and methods of formation thereof are disclosed. A first barrier material is deposited on top surfaces of an insulating material, and a second barrier material is deposited on sidewalls of the insulating material, wherein the second barrier material is different than the first barrier material. The first barrier material induces grain growth of a subsequently deposited conductive material at a first rate, and the second barrier material induces grain growth of the conductive material at a second rate, wherein the second rate is slower than the first rate.

Abstract translation: 公开了用于导电特征的阻挡层及其形成方法。 第一阻挡材料沉积在绝缘材料的顶表面上，并且第二阻挡材料沉积在绝缘材料的侧壁上，其中第二阻挡材料不同于第一阻挡材料。 第一阻挡材料以第一速率诱导随后沉积的导电材料的晶粒生长，并且第二阻挡材料以第二速率诱导导电材料的晶粒生长，其中第二速率比第一速率慢。