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公开(公告)号：US20230411253A1
公开(公告)日：2023-12-21
申请号：US18185865
申请日：2023-03-17
IPC分类号： H01L23/495 , H01L23/31 , H02M7/5387 , H01L21/56
CPC分类号： H01L23/49548 , H01L23/3107 , H01L23/49562 , H02M7/53875 , H01L21/565
摘要： Even if there is a change in the shape of a transfer mold power module is required, a change in a position of the electrode of the module is facilitated by separating electrode terminals of a power module from the electrodes and retrofitting the separated electrode terminals to the electrodes with high precision. A semiconductor device includes a mold resin enclosing a semiconductor chip, an electrode electrically connected to the semiconductor chip and exposed in an opening provided in the mold resin, and an electrode terminal having a contact portion that covers the electrode and is in electrical contact with the electrode, a plurality of projections formed to surround the contact portion and provided between a side surface of the opening and the contact portion, a contact end portion having the contact portion and an open end portion which is a different end portion from the contact end portion.
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公开(公告)号：US20170294369A1
公开(公告)日：2017-10-12
申请号：US15508118
申请日：2014-11-07
发明人： Hiroshi KAWASHIMA , Ken SAKAMOTO , Satoshi KONDO , Taketoshi SHIKANO , Yoshihiro TAKAI , Claudio FELICIANI
IPC分类号： H01L23/495 , H01L23/00 , H01L23/31 , H01L21/56 , H01L23/498
CPC分类号： H01L23/49537 , H01L21/565 , H01L23/3107 , H01L23/49503 , H01L23/49513 , H01L23/49541 , H01L23/49551 , H01L23/49555 , H01L23/49558 , H01L23/49568 , H01L23/49861 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/85 , H01L25/07 , H01L25/18 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48108 , H01L2224/48137 , H01L2224/48245 , H01L2224/48247 , H01L2224/4903 , H01L2224/49171 , H01L2224/73265 , H01L2924/181 , H01L2924/19105 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： A power semiconductor device includes a power semiconductor element, a controlling element, a first lead frame and a second lead frame, respectively, a first metal wire electrically connecting the power semiconductor element and the first lead frame, and a sealing body covering these components. The first lead frame includes a first inner lead having a connecting surface to which one end of the first metal wire is connected. Among surfaces of the sealing body, in a side surface, a resin inlet mark is formed in a side surface portion from which the first lead frame and the second lead frame do not project, the resin inlet mark being greater in surface roughness than another area. The resin inlet mark is formed opposite to a side where the first metal wire is positioned on the connecting surface when seen in the direction along the mounting surface.
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公开(公告)号：US20200091047A1
公开(公告)日：2020-03-19
申请号：US16686971
申请日：2019-11-18
IPC分类号： H01L23/495 , H01L21/56 , H01L21/48 , H01L23/00
摘要： A first lead terminal, a second lead terminal provided parallel to the first lead terminal, and a tie bar connecting the first lead terminal and the second lead terminal are provided. The tie bar includes a first narrow-width section touching the first lead terminal, a second narrow-width section touching the second lead terminal, and a wide-width section having a larger width than the first narrow-width section and the second narrow-width section and connecting the first narrow-width section and the second narrow-width section. The wide-width section has a through-hole formed between the first narrow-width section and the second narrow-width section.
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公开(公告)号：US20160343644A1
公开(公告)日：2016-11-24
申请号：US15112890
申请日：2014-05-12
IPC分类号： H01L23/495 , H01L23/00 , H01L23/31 , H01L21/48 , H01L21/56
CPC分类号： H01L24/49 , H01L21/565 , H01L23/3107 , H01L23/4334 , H01L23/49537 , H01L23/49551 , H01L23/49562 , H01L23/49575 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L2224/291 , H01L2224/2929 , H01L2224/293 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48108 , H01L2224/48137 , H01L2224/48247 , H01L2224/48257 , H01L2224/49052 , H01L2224/49171 , H01L2224/49505 , H01L2224/73265 , H01L2924/10161 , H01L2924/13055 , H01L2924/181 , H01L2924/1815 , H01L2924/3511 , H01L2924/00012 , H01L2924/00014 , H01L2924/014 , H01L2924/00
摘要： A power semiconductor element is fixed on a die pad of the lead frame. A metal plate is bonded to a lower surface of the die pad via an insulating film. The inner lead etc. are disposed in a cavity between a lower mold and an upper mold and are encapsulated with an encapsulation resin. The lower mold has a stepped portion provided in a bottom surface of the cavity below the inner lead. A height of an upper surface of the stepped portion is larger than a height of an upper surface of the power semiconductor element disposed in the cavity. When an encapsulation resin is injected into the cavity, a lower surface of the metal plate is in contact with the bottom surface of the cavity, and the encapsulation resin flows downward from above the stepped portion toward the upper surface of the power semiconductor element.
摘要翻译： 功率半导体元件固定在引线框的芯片焊盘上。 金属板经由绝缘膜与芯片焊盘的下表面接合。 内引线等设置在下模和上模之间的空腔中，并用封装树脂封装。 下模具有设置在内引线下方的空腔的底表面中的台阶部分。 阶梯部的上表面的高度大于设置在空腔中的功率半导体元件的上表面的高度。 当封装树脂注入到空腔中时，金属板的下表面与空腔的底表面接触，并且封装树脂从台阶部分的上方朝着功率半导体元件的上表面向下流动。
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公开(公告)号：US20230187308A1
公开(公告)日：2023-06-15
申请号：US17857293
申请日：2022-07-05
发明人： Masanori TSUKUDA , Koichi NISHI , Shinya SONEDA , Koji TANAKA , Norikazu SAKAI , Taketoshi SHIKANO
IPC分类号： H01L23/373 , H01L23/00
CPC分类号： H01L23/3735 , H01L24/48 , H01L2224/48225 , H01L2924/13055
摘要： A first principal electrode and a first control electrode pad are formed on a first principal surface of the semiconductor chip. A second principal electrode and a second control electrode pad are formed on a second principal surface of the semiconductor chip. The second principal electrode and the second control electrode pad are respectively bonded to first and second metal patterns of an insulating substrate. Bonding sections of first and second wires overlap a bonding section of the second principal electrode or the second control electrode pad in plan view. Thickness of the first and second metal patterns is 0.2 mm or less.
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公开(公告)号：US20200303295A1
公开(公告)日：2020-09-24
申请号：US16738634
申请日：2020-01-09
IPC分类号： H01L23/498 , H01L21/48
摘要： Provided are a power semiconductor device using a lead frame, in which deformation and bending of terminals is suppressed, insulation is secured between terminals, and mounting onto a control board is facilitated, and a manufacturing method thereof. A package in which a semiconductor element mounted on a lead frame is sealed, terminals being bent and exposed from side surfaces of the package, and, a terminal bending portion being a portion bent in each of the terminals, a width thereof being larger than a width of a tip of the terminal, and being equal to or smaller than the width of a contact portion of the terminal in contact with the package are provided; therefore, deformation and bending of the terminals is suppressed, a necessary insulation is secured between the adjacent terminals, and mounting onto a control board is facilitated.
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公开(公告)号：US20160233151A1
公开(公告)日：2016-08-11
申请号：US15021413
申请日：2014-01-10
IPC分类号： H01L23/495 , H01L23/31
CPC分类号： H01L23/49568 , H01L23/3107 , H01L23/3114 , H01L23/49503 , H01L23/4952 , H01L23/49531 , H01L23/49537 , H01L23/49562 , H01L23/49575 , H01L23/49582 , H01L25/07 , H01L25/18 , H01L2224/48137 , H01L2224/48139 , H01L2224/48247 , H01L2224/4903 , H01L2224/49111 , H01L2924/0002 , H01L2924/00
摘要： An object is to provide a technique in which a cost reduction in a power semiconductor device can be achieved while maintaining heat dissipation performance as much as possible. A power semiconductor device includes a leadframe, a power semiconductor element disposed on an upper surface of the leadframe, and an insulating layer disposed on a lower surface of the leadframe. At least a partial line of a peripheral line of a region where the insulating layer is disposed, on the lower surface, is aligned, in top view, with at least a partial line of an expanded peripheral line obtained by shifting outwardly, by the amount corresponding to the thickness of the leadframe, the peripheral line of the region where the power semiconductor element is disposed, on the upper surface.
摘要翻译： 本发明的目的是提供一种可以在尽可能多地保持散热性能的同时实现功率半导体器件的成本降低的技术。 功率半导体器件包括引线框架，设置在引线框架的上表面上的功率半导体元件以及设置在引线框架的下表面上的绝缘层。 至少在下表面上设置有绝缘层的区域的外围线的部分线在顶视图中与通过向外偏移获得的至少一个扩展的周边线的部分线对齐， 对应于引线框的厚度，即设置有功率半导体元件的区域的外围线，在上表面上。
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公开(公告)号：US20150092379A1
公开(公告)日：2015-04-02
申请号：US14269585
申请日：2014-05-05
发明人： Naoki YOSHIMATSU , Masayoshi SHINKAI , Taketoshi SHIKANO , Daisuke MURATA , Nobuyoshi KIMOTO , Yuji IMOTO , Mikio ISHIHARA
CPC分类号： H05K1/18 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/13055 , H05K1/0203 , H05K1/0306 , H05K3/06 , H05K3/20 , H05K3/284 , H05K2201/0373 , H05K2201/09036 , H05K2203/049 , H05K2203/1184 , H05K2203/1316 , Y10T29/41 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device according to the present invention includes a ceramic substrate, a plurality of circuit patterns arranged on a surface of the ceramic substrate, a semiconductor element arranged on an upper surface of at least one circuit pattern, and a sealing resin for sealing the ceramic substrate, the plurality of circuit patterns, and the semiconductor element, in which an undercut part is formed in opposed side surfaces of the circuit patterns adjacent to one another, the undercut part is configured such that an end of an upper surface of the circuit pattern protrudes outside the circuit pattern more than an end of a lower surface of the circuit pattern on the ceramic substrate, and the undercut part is also filled with the sealing resin.
摘要翻译： 根据本发明的半导体器件包括陶瓷衬底，布置在陶瓷衬底的表面上的多个电路图案，布置在至少一个电路图案的上表面上的半导体元件和用于密封陶瓷的密封树脂 衬底，多个电路图案和半导体元件，其中在相邻的电路图案的相对侧表面中形成底切部分，底切部分被构造成使得电路图案的上表面的端部 突出在电路图案之外的多于陶瓷基板上的电路图案的下表面的端部，并且底切部分也填充有密封树脂。
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公开(公告)号：US20240047318A1
公开(公告)日：2024-02-08
申请号：US18315540
申请日：2023-05-11
发明人： Yosuke NAKATA , Yuji SATO , Taketoshi SHIKANO
IPC分类号： H01L23/495 , H01L23/00 , H01L23/31 , H01L23/053 , H01L25/07 , H01L25/00 , H01L21/56 , H01L21/66
CPC分类号： H01L23/49575 , H01L23/49562 , H01L24/40 , H01L23/3135 , H01L23/053 , H01L25/072 , H01L25/50 , H01L21/56 , H01L22/14 , H01L2224/40139 , H01L2224/48175 , H01L24/48 , H01L2224/73221 , H01L24/73
摘要： An object is to provide a technique capable of reducing stress in the entire semiconductor device. The semiconductor device includes a plurality of sub-modules including a first sealing member, an insulating substrate provided with a first circuit pattern electrically connected to at least one of the conductive plates of the plurality of sub-modules, connection members electrically connected to at least one of the conductive pieces of the plurality of sub-modules, and a second sealing member having lower hardness than the first sealing member, which seals the plurality of sub-modules, the insulating substrate, and the connection members.
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公开(公告)号：US20230335480A1
公开(公告)日：2023-10-19
申请号：US18339149
申请日：2023-06-21
IPC分类号： H01L23/498 , H01L21/48
CPC分类号： H01L23/49838 , H01L21/4842 , H01L23/49861
摘要： Provided are a power semiconductor device using a lead frame, in which deformation and bending of terminals is suppressed, insulation is secured between terminals, and mounting onto a control board is facilitated, and a manufacturing method thereof. A package in which a semiconductor element mounted on a lead frame is sealed, terminals being bent and exposed from side surfaces of the package, and, a terminal bending portion being a portion bent in each of the terminals, a width thereof being larger than a width of a tip of the terminal, and being equal to or smaller than the width of a contact portion of the terminal in contact with the package are provided; therefore, deformation and bending of the terminals is suppressed, a necessary insulation is secured between the adjacent terminals, and mounting onto a control board is facilitated.
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