公开(公告)号：US20150380386A1

公开(公告)日：2015-12-31

申请号：US14316580

申请日：2014-06-26

申请人： MICHAEL B. VINCENT ,  SCOTT M. HAYES

发明人： MICHAEL B. VINCENT ,  SCOTT M. HAYES

IPC分类号： H01L25/065 ,  H01L21/56 ,  H01L23/528 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L21/78

CPC分类号： H01L25/0657 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/528 ,  H01L23/5389 ,  H01L24/09 ,  H01L24/19 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06551 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2924/35

摘要： Methods for fabricating microelectronic packages and microelectronic packages are provided. In one embodiment, the microelectronic package fabrication method includes producing a molded panel containing a sidewall substrate. The molded panel is singulated to produce a Fan-Out Wafer Level Package core including a molded body having a fan-out region in which the sidewall substrate is embedded. A side connect trace is printed or otherwise formed on a sidewall of the Fan-Out Wafer Level Package core and extends at least partially across the embedded sidewall substrate.

摘要翻译： 提供了制造微电子封装和微电子封装的方法。 在一个实施例中，微电子封装制造方法包括制造包含侧壁基板的模制板。 将模制板分割成产生扇出晶片级封装芯，该芯包括具有嵌入侧壁基板的扇出区域的成型体。 侧面连接迹线印刷或以其它方式形成在扇出晶片级封装芯的侧壁上，并且至少部分地延伸穿过嵌入的侧壁基板。

公开(公告)号：US20150162309A1

公开(公告)日：2015-06-11

申请号：US14097424

申请日：2013-12-05

申请人： MICHAEL B. VINCENT ,  SCOTT M. HAYES

发明人： MICHAEL B. VINCENT ,  SCOTT M. HAYES

IPC分类号： H01L25/065 ,  H01L23/29 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/528 ,  H01L23/53204 ,  H01L23/5328 ,  H01L23/5329 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2225/1076 ,  H01L2924/12042 ,  H01L2924/1815 ,  H01L2924/00

摘要： Embodiments of methods for forming a device include performing an oxidation inhibiting treatment to exposed ends of first and second device-to-edge conductors, and forming a package surface conductor to electrically couple the exposed ends of the first and second device-to-edge conductors. Performing the oxidation inhibiting treatment may include applying an organic solderability protectant coating to the exposed ends, or plating the exposed ends with a conductive plating material. The method may further include applying a conformal protective coating over the package surface conductor. An embodiment of a device formed using such a method includes a package body, the first and second device-to-edge conductors, the package surface conductor on a surface of the package body and extending between the first and second device-to-edge conductors, and the conformal protective coating over the package surface conductor.

摘要翻译： 用于形成装置的方法的实施例包括对第一和第二器件对边缘导体的暴露端执行氧化抑制处理，以及形成封装表面导体，以电耦合第一和第二器件对边缘导体的暴露端 。 执行氧化抑制处理可以包括将有机可焊性保护剂涂层施加到暴露端，或者用导电电镀材料电镀暴露端。 该方法还可以包括在包装表面导体上施加保形涂层。 使用这种方法形成的器件的实施例包括封装体，第一和第二器件对边缘导体，封装体表面上的封装表面导体，并且在第一和第二器件对边缘导体之间延伸 ，以及封装表面导体上的保形涂层。

公开(公告)号：US20150270233A1

公开(公告)日：2015-09-24

申请号：US14223805

申请日：2014-03-24

申请人： MICHAEL B. VINCENT ,  TRUNG Q. DUONG ,  ZHIWEI GONG ,  SCOTT M. HAYES ,  ALAN J. MAGNUS ,  DOUGLAS G. MITCHELL ,  EDUARD J. PABST ,  JASON R. WRIGHT ,  WENG F. YAP

发明人： MICHAEL B. VINCENT ,  TRUNG Q. DUONG ,  ZHIWEI GONG ,  SCOTT M. HAYES ,  ALAN J. MAGNUS ,  DOUGLAS G. MITCHELL ,  EDUARD J. PABST ,  JASON R. WRIGHT ,  WENG F. YAP

IPC分类号： H01L23/00

CPC分类号： H01L24/02 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/564 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/96 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2924/014

摘要： Wafer level packages and methods for producing wafer level packages having delamination-resistant redistribution layers are provided. In one embodiment, the method includes building inner redistribution layers over a semiconductor die. Inner redistribution layers include a body of dielectric material containing metal routing features. A routing-free dielectric block is formed in the body of dielectric material and is uninterrupted by the metal routing features. An outer redistribution layer is produced over the inner redistribution layers and contains a metal plane, which is patterned to include one or more outgassing openings overlying the routing-free dielectric block. The routing-free dielectric block has a minimum width, length, and depth each at least twice the thickness of the outer redistribution layer.

摘要翻译： 提供了晶片级封装以及用于生产具有防分层再分配层的晶片级封装的方法。 在一个实施例中，该方法包括在半导体管芯上建立内部再分布层。 内部再分布层包括含有金属布线特征的绝缘材料体。 在电介质材料的主体中形成无路由的介质块，并且不被金属布线特征中断。 外再分布层在内再分布层上产生并且包含金属平面，其被图案化以包括覆盖无路由介质块的一个或多个除气开口。 无路由介质块具有最小宽度，长度和深度，每个至少两倍于外再分布层的厚度。

公开(公告)号：US20150243635A1

公开(公告)日：2015-08-27

申请号：US14706359

申请日：2015-05-07

申请人： MICHAEL B. VINCENT ,  SCOTT M. HAYES ,  JASON R. WRIGHT ,  ZHIWEI GONG

发明人： MICHAEL B. VINCENT ,  SCOTT M. HAYES ,  JASON R. WRIGHT ,  ZHIWEI GONG

IPC分类号： H01L25/065 ,  H01L23/31

CPC分类号： H01L25/0657 ,  H01L21/4853 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L25/03 ,  H01L25/105 ,  H01L25/50 ,  H01L2225/06551 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/00

摘要： Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of stacked microelectronic packages. In one embodiment, the method includes producing a partially-completed stacked microelectronic package including a package body having a vertical package sidewall, a plurality microelectronic devices embedded within the package body, and package edge conductors electrically coupled to the plurality of microelectronic devices and extending to the vertical package sidewall. A flowable conductive material is applied on the vertical package sidewall and contacts the package edge conductors. Selected portions of the flowable conductive material are then removed to define, at least in part, electrically-isolated sidewall conductors electrically coupled to different ones of the package edge conductors.

摘要翻译： 提供了用于制造堆叠的微电子封装的方法的实施例，如堆叠的微电子封装的实施例。 在一个实施例中，该方法包括产生部分完成的叠层微电子封装，其包括具有垂直封装侧壁的封装体，嵌入封装主体内的多个微电子器件，以及电耦合到多个微电子器件的封装边缘导体， 垂直封装侧壁。 可流动的导电材料施加在垂直封装侧壁上，并与封装边缘导体接触。 然后去除可流动导电材料的选定部分，以至少部分地限定电隔离的侧壁导体，其电耦合到不同的封装边缘导体。

公开(公告)号：US20150348865A1

公开(公告)日：2015-12-03

申请号：US14291547

申请日：2014-05-30

申请人： MICHAEL B. VINCENT ,  SCOTT M. HAYES

发明人： MICHAEL B. VINCENT ,  SCOTT M. HAYES

IPC分类号： H01L23/367 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

CPC分类号： H01L24/32 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3672 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/58 ,  H01L24/03 ,  H01L24/09 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/83 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01L2223/6677 ,  H01L2224/0231 ,  H01L2224/0237 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2731 ,  H01L2224/32175 ,  H01L2224/73267 ,  H01L2224/8384 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2225/1094 ,  H01L2924/18162 ,  H01L2924/3025

摘要： Microelectronic packages and methods for producing microelectronic packages having sidewall-deposited heat spreader structures are provided. In one embodiment, the method includes providing a package body containing a microelectronic device. A heat spreader structure is printed or otherwise formed over at least one sidewall of the package body. The heat spreader structure is thermally coupled to the microelectronic device and is configured to dissipate heat generated thereby during operation of the microelectronic package.

摘要翻译： 提供了微电子封装和用于制造具有侧壁沉积的散热器结构的微电子封装的方法。 在一个实施例中，该方法包括提供包含微电子器件的封装主体。 在包装体的至少一个侧壁上印刷或以其它方式形成散热器结构。 散热器结构热耦合到微电子器件，并且被配置为在微电子封装的操作期间散发由此产生的热量。

公开(公告)号：US20160073496A1

公开(公告)日：2016-03-10

申请号：US14477729

申请日：2014-09-04

申请人： MICHAEL B. VINCENT

发明人： MICHAEL B. VINCENT

IPC分类号： H05K1/02 ,  H05K1/18 ,  H05K3/46 ,  H05K3/10 ,  H01L23/00 ,  H01L23/552 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H05K1/11 ,  H05K3/00

CPC分类号： H05K1/0298 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/552 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/12105 ,  H01L2924/19105 ,  H05K1/0218 ,  H05K1/115 ,  H05K1/181 ,  H05K3/0073 ,  H05K3/10 ,  H05K3/4644 ,  H05K2201/0715 ,  Y10T29/4913

摘要： Fan-Out Wafer Level Packages (FO-WLPs) and methods for fabricating FO-WLPs having Embedded Ground Plane (EGP) connections are provided. In one embodiment, the method includes forming a molded panel around an EGP array from which a plurality of preformed EGP connections project. One or more Redistribution Layers (RDLs) are produced over the molded panel. The molded panel is then singulated to yield a plurality of FO-WLPs each including a molded package body containing an EGP from the EGP array and one or more of preformed EGP connections.

摘要翻译： 提供扇形晶圆级封装（FO-WLP）和制造具有嵌入式地平面（EGP）连接的FO-WLP的方法。 在一个实施例中，该方法包括在EGP阵列周围形成模制板，多个预成型的EGP连接从该EGP阵列突出。 在模制面板上生产一个或多个再分配层（RDL）。 然后将模制板分割成多个FO-WLP，每个FO-WLP包括来自EGP阵列的包含EGP的模制封装主体和一个或多个预先形成的EGP连接。

公开(公告)号：US20150262931A1

公开(公告)日：2015-09-17

申请号：US14210057

申请日：2014-03-13

申请人： MICHAEL B. VINCENT ,  ZHIWEI GONG ,  JASON R. WRIGHT

发明人： MICHAEL B. VINCENT ,  ZHIWEI GONG ,  JASON R. WRIGHT

IPC分类号： H01L23/528 ,  H01L21/56 ,  H01L23/66 ,  H01L23/31 ,  H01L25/00 ,  H01L25/16 ,  H01L21/768 ,  H01L21/78

CPC分类号： H01L23/66 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/76838 ,  H01L21/76841 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/49816 ,  H01L23/49883 ,  H01L23/5328 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/24145 ,  H01L2224/24195 ,  H01L2224/24225 ,  H01L2224/24227 ,  H01L2224/32145 ,  H01L2224/32153 ,  H01L2224/32221 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19105

摘要： Methods for fabricating microelectronic packages, such as Fan-Out Wafer Level Packages, and microelectronic packages are provided. In one embodiment, the method includes placing a first semiconductor die on a temporary substrate, forming an electrically-conducive trace in contact with at least one of the first semiconductor die and the temporary substrate, and encapsulating the first semiconductor die and the electrically-conductive trace within a molded panel. The temporary substrate is removed to reveal a frontside of the molded panel through which the electrically-conducive trace is at least partially exposed. At least one redistribution layer is formed over the frontside of the molded panel, the at least one redistribution layer comprises an interconnect line in ohmic contact with the electrically-conducive trace.

摘要翻译： 提供了制造微电子封装的方法，例如扇出晶片级封装和微电子封装。 在一个实施例中，该方法包括将第一半导体管芯放置在临时衬底上，形成与第一半导体管芯和临时衬底中的至少一个接触的导电迹线，以及封装第一半导体管芯和导电 在模制面板内追踪。 去除临时衬底以露出模制面板的前侧，电导体迹线至少部分地暴露在模制面板的前侧。 在模制面板的前侧形成至少一个再分布层，所述至少一个再分配层包括与导电迹线欧姆接触的互连线。

公开(公告)号：US20160013076A1

公开(公告)日：2016-01-14

申请号：US14330971

申请日：2014-07-14

申请人： MICHAEL B. VINCENT ,  ZHIWEI GONG

发明人： MICHAEL B. VINCENT ,  ZHIWEI GONG

IPC分类号： H01L21/56 ,  H01L25/10 ,  H01L21/78

CPC分类号： H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/16 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/105 ,  H01L25/50 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/8203 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/1434 ,  H01L2224/83005

摘要： Three dimensional (3D) package assembly and methods for producing 3D package assembly are provided. In one embodiment, the method includes positioning a first plurality of microelectronic devices on a pre-singulated substrate package array. The microelectronic devices can be, for example, semiconductor; and the pre-singulated substrate package array can be a molded substrate panel. The first plurality of microelectronic devices is encapsulated while supported by the pre-singulated substrate package array to produce a direct-built panel containing the first plurality of microelectronic devices. The direct-built panel and the pre-singulated substrate package array are then singulated to yield a plurality of 3D package assemblies each comprised of a substrate package and a direct-built package. The direct-built package is bonded to the substrate package and containing at least one of the first plurality of microelectronic devices.

摘要翻译： 提供三维（3D）封装组件和用于生产3D封装组件的方法。 在一个实施例中，该方法包括将第一多个微电子器件定位在预分割的衬底封装阵列上。 微电子器件可以是例如半导体; 并且预分割衬底封装阵列可以是模制衬底面板。 第一多个微电子器件被预先分割的衬底封装阵列支持时封装，以产生包含第一多个微电子器件的直接构建的面板。 然后将直接制造的面板和预分割的衬底封装阵列分离，以产生多个3D封装组件，每个3D封装组件由衬底封装和直接构建的封装构成。 直接构建的封装结合到衬底封装并且包含第一多个微电子器件中的至少一个。

公开(公告)号：US20150108661A1

公开(公告)日：2015-04-23

申请号：US14056844

申请日：2013-10-17

申请人： MICHAEL B. VINCENT

发明人： MICHAEL B. VINCENT

IPC分类号： H01L23/00 ,  H01L23/538 ,  H01L21/78 ,  H01L23/28

CPC分类号： H01L24/30 ,  H01L21/568 ,  H01L21/78 ,  H01L23/28 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/29347 ,  H01L2224/3001 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/83851 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00

摘要： Microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the method includes encapsulating a device stack within a molded panel having a frontside and a backside. The device stack contains an upper semiconductor die and an interconnect buffer layer, which is formed over the upper semiconductor die and which is covered by the frontside of the molded panel. Material is removed from the frontside the molded panel to expose the interconnect buffer layer therethrough. One or more frontside redistribution layers are produced over the frontside of the molded panel and electrically coupled to the upper semiconductor die through the interconnect buffer layer. The molded panel is then singulated to yield a microelectronic package including a molded package body containing the device stack.

摘要翻译： 提供了用于制造微电子封装的微电子封装和方法。 在一个实施例中，该方法包括将装置堆叠封装在具有前侧和后侧的模制面板内。 器件堆叠包含上半导体管芯和互连缓冲层，其形成在上半导体管芯上方并且被模制面板的前侧覆盖。 材料从模制板的前侧移除，以使互连缓冲层暴露于其间。 在模制面板的前侧产生一个或多个前沿再分配层，并通过互连缓冲层电耦合到上半导体管芯。 然后将模制板分割成微电子封装，其包括包含器件堆叠的模制封装主体。

公开(公告)号：US20150092372A1

公开(公告)日：2015-04-02

申请号：US14042623

申请日：2013-09-30

申请人： MICHAEL B. VINCENT ,  Zhiwei Gong

发明人： MICHAEL B. VINCENT ,  Zhiwei Gong

IPC分类号： H05K1/11 ,  H05K3/10 ,  H05K3/32 ,  H05K1/18

CPC分类号： H01L23/3114 ,  H01L23/49805 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2225/1076 ,  H01L2924/12042 ,  H01L2924/1815 ,  Y10T29/4913 ,  H01L2924/00

摘要： Embodiments of devices and methods of their manufacture include coupling first and second package surface conductors to a package surface with an intra-conductor insulating structure between the package surface conductors. The package surface conductors extend between and electrically couple sets of pads that are exposed at the package surface. Elongated portions of the package surface conductors are parallel with and adjacent to each other. The intra-conductor insulating structure is coupled between the package surface conductors along an entirety of the parallel and adjacent elongated portions, and the intra-conductor insulating structure electrically insulates the elongated portions of the package surface conductors from each other. Some embodiments may be implemented in conjunction with a stacked microelectronic package that includes sidewall conductors and an intra-conductor insulating structure between and electrically insulating the sidewall conductors from each other.

摘要翻译： 装置及其制造方法的实施例包括将第一和第二封装表面导体耦合到封装表面，并在封装表面导体之间具有导体内绝缘结构。 封装表面导体在封装表面露出的焊垫组之间延伸并电耦合。 包装表面导体的细长部分彼此平行并相邻。 导体内绝缘结构沿着整个平行和相邻的细长部分耦合在封装表面导体之间，并且导体内绝缘结构将封装表面导体的细长部分彼此电绝缘。 一些实施例可以结合堆叠的微电子封装来实现，该堆叠式微电子封装包括侧壁导体和导体间绝缘结构，并且使侧壁导体彼此电绝缘。