公开(公告)号：US20150092372A1

公开(公告)日：2015-04-02

申请号：US14042623

申请日：2013-09-30

申请人： MICHAEL B. VINCENT ,  Zhiwei Gong

发明人： MICHAEL B. VINCENT ,  Zhiwei Gong

IPC分类号： H05K1/11 ,  H05K3/10 ,  H05K3/32 ,  H05K1/18

CPC分类号： H01L23/3114 ,  H01L23/49805 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2225/1076 ,  H01L2924/12042 ,  H01L2924/1815 ,  Y10T29/4913 ,  H01L2924/00

摘要： Embodiments of devices and methods of their manufacture include coupling first and second package surface conductors to a package surface with an intra-conductor insulating structure between the package surface conductors. The package surface conductors extend between and electrically couple sets of pads that are exposed at the package surface. Elongated portions of the package surface conductors are parallel with and adjacent to each other. The intra-conductor insulating structure is coupled between the package surface conductors along an entirety of the parallel and adjacent elongated portions, and the intra-conductor insulating structure electrically insulates the elongated portions of the package surface conductors from each other. Some embodiments may be implemented in conjunction with a stacked microelectronic package that includes sidewall conductors and an intra-conductor insulating structure between and electrically insulating the sidewall conductors from each other.

摘要翻译： 装置及其制造方法的实施例包括将第一和第二封装表面导体耦合到封装表面，并在封装表面导体之间具有导体内绝缘结构。 封装表面导体在封装表面露出的焊垫组之间延伸并电耦合。 包装表面导体的细长部分彼此平行并相邻。 导体内绝缘结构沿着整个平行和相邻的细长部分耦合在封装表面导体之间，并且导体内绝缘结构将封装表面导体的细长部分彼此电绝缘。 一些实施例可以结合堆叠的微电子封装来实现，该堆叠式微电子封装包括侧壁导体和导体间绝缘结构，并且使侧壁导体彼此电绝缘。

公开(公告)号：US09331029B2

公开(公告)日：2016-05-03

申请号：US14210057

申请日：2014-03-13

申请人： Michael B. Vincent ,  Zhiwei Gong ,  Jason R. Wright

发明人： Michael B. Vincent ,  Zhiwei Gong ,  Jason R. Wright

IPC分类号： H01L21/44 ,  H01L23/66 ,  H01L21/768 ,  H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L25/00 ,  H01L25/16 ,  H01L21/48 ,  H01L23/538 ,  H01L21/683 ,  H01L23/498 ,  H01L23/532

CPC分类号： H01L23/66 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/76838 ,  H01L21/76841 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/49816 ,  H01L23/49883 ,  H01L23/5328 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/24145 ,  H01L2224/24195 ,  H01L2224/24225 ,  H01L2224/24227 ,  H01L2224/32145 ,  H01L2224/32153 ,  H01L2224/32221 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19105

摘要： Methods for fabricating microelectronic packages, such as Fan-Out Wafer Level Packages, and microelectronic packages are provided. In one embodiment, the method includes placing a first semiconductor die on a temporary substrate, forming an electrically-conducive trace in contact with at least one of the first semiconductor die and the temporary substrate, and encapsulating the first semiconductor die and the electrically-conductive trace within a molded panel. The temporary substrate is removed to reveal a frontside of the molded panel through which the electrically-conducive trace is at least partially exposed. At least one redistribution layer is formed over the frontside of the molded panel, the at least one redistribution layer comprises an interconnect line in ohmic contact with the electrically-conducive trace.

摘要翻译： 提供了制造微电子封装的方法，例如扇出晶片级封装和微电子封装。 在一个实施例中，该方法包括将第一半导体管芯放置在临时衬底上，形成与第一半导体管芯和临时衬底中的至少一个接触的导电迹线，以及封装第一半导体管芯和导电 在模制面板内追踪。 去除临时衬底以露出模制面板的前侧，电导体迹线至少部分地暴露在模制面板的前侧。 在模制面板的前侧形成至少一个再分布层，所述至少一个再分配层包括与导电迹线欧姆接触的互连线。

公开(公告)号：US20150115454A1

公开(公告)日：2015-04-30

申请号：US14067809

申请日：2013-10-30

申请人： Alan J. Magnus ,  Trung Q. Duong ,  Zhiwei Gong ,  Scott M. Hayes ,  Douglas G. Mitchell ,  Michael B. Vincent ,  Jason R. Wright ,  Weng F. Yap

发明人： Alan J. Magnus ,  Trung Q. Duong ,  Zhiwei Gong ,  Scott M. Hayes ,  Douglas G. Mitchell ,  Michael B. Vincent ,  Jason R. Wright ,  Weng F. Yap

IPC分类号： H01L23/00 ,  H01L21/768

CPC分类号： H01L24/97 ,  H01L21/568 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/19

摘要： Microelectronic packages having layered interconnect structures are provided, as are methods for the fabrication thereof. In one embodiment, the method includes forming a first plurality of interconnect lines in ohmic contact with a first bond pad row provided on a semiconductor. A dielectric layer is deposited over the first plurality of interconnect lines, the first bond pad row, and a second bond pad row adjacent the first bond pad row. A trench via is then formed in the dielectric layer to expose at least the second bond pad row therethrough. A second plurality of interconnect lines is formed in ohmic contact with the second bond pad row within the trench via. The second plurality of interconnect lines extends over the first bond pad row and is electrically isolated therefrom by the dielectric layer to produce at least a portion of the layered interconnect structure.

摘要翻译： 提供具有分层互连结构的微电子封装，以及制造它们的方法。 在一个实施例中，该方法包括形成与设置在半导体上的第一接合焊盘排欧姆接触的第一多个互连线。 介电层沉积在第一多个互连线上，第一接合焊盘行和与第一接合焊盘行相邻的第二接合焊盘排。 然后在电介质层中形成沟槽通孔，以至少暴露第二接合焊盘排。 第二多个互连线形成为与沟槽通孔内的第二接合焊盘排欧姆接触。 所述第二多个互连线延伸穿过所述第一接合焊盘行并且通过所述电介质层与其电隔离以产生所述分层互连结构的至少一部分。

公开(公告)号：US09520323B2

公开(公告)日：2016-12-13

申请号：US13610488

申请日：2012-09-11

申请人： Michael B Vincent ,  Zhiwei Gong ,  Scott M Hayes ,  Douglas G Mitchell

发明人： Michael B Vincent ,  Zhiwei Gong ,  Scott M Hayes ,  Douglas G Mitchell

IPC分类号： H01L23/52 ,  H01L21/768 ,  H01L23/528 ,  H01L23/00 ,  H01L23/485 ,  H01L23/525

CPC分类号： H01L21/76816 ,  H01L21/76814 ,  H01L23/485 ,  H01L23/525 ,  H01L23/528 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/0231 ,  H01L2224/02375 ,  H01L2224/04105 ,  H01L2924/12042 ,  H01L2924/00

摘要： Embodiments of a microelectronic package including at least one trench via are provided, as are embodiments of a method for fabricating such a microelectronic package. In one embodiment, the method includes the step of depositing a dielectric layer over a first microelectronic device having a plurality of contact pads, which are covered by the dielectric layer. A trench via is formed in the dielectric layer to expose the plurality of contact pads therethrough. The trench via is formed to include opposing crenulated sidewalls having a plurality of recesses therein. The plurality of contact pads exposed through the trench via are then sputter etched. A plurality of interconnect lines is formed over the dielectric layer, each of which is electrically coupled to a different one of the plurality of contact pads.

摘要翻译： 提供了包括至少一个沟槽通孔的微电子封装的实施例，如制造这种微电子封装的方法的实施例。 在一个实施例中，该方法包括在第一微电子器件上沉积介电层的步骤，该第一微电子器件具有被介电层覆盖的多个接触焊盘。 沟槽通孔形成在电介质层中以暴露多个接触焊盘。 沟槽通孔被形成为包括在其中具有多个凹部的相对的有齿的侧壁。 然后溅射蚀刻通过沟槽通孔暴露的多个接触焊盘。 多个互连线形成在电介质层上，每个互连线电耦合到多个接触焊盘中的不同的一个。

公开(公告)号：US09502363B2

公开(公告)日：2016-11-22

申请号：US14223805

申请日：2014-03-24

申请人： Michael B. Vincent ,  Trung Q. Duong ,  Zhiwei Gong ,  Scott M. Hayes ,  Alan J. Magnus ,  Douglas G. Mitchell ,  Eduard J. Pabst ,  Jason R. Wright ,  Weng F. Yap

发明人： Michael B. Vincent ,  Trung Q. Duong ,  Zhiwei Gong ,  Scott M. Hayes ,  Alan J. Magnus ,  Douglas G. Mitchell ,  Eduard J. Pabst ,  Jason R. Wright ,  Weng F. Yap

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC分类号： H01L24/02 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/564 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/96 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2924/014

摘要： Wafer level packages and methods for producing wafer level packages having delamination-resistant redistribution layers are provided. In one embodiment, the method includes building inner redistribution layers over a semiconductor die. Inner redistribution layers include a body of dielectric material containing metal routing features. A routing-free dielectric block is formed in the body of dielectric material and is uninterrupted by the metal routing features. An outer redistribution layer is produced over the inner redistribution layers and contains a metal plane, which is patterned to include one or more outgassing openings overlying the routing-free dielectric block. The routing-free dielectric block has a minimum width, length, and depth each at least twice the thickness of the outer redistribution layer.

摘要翻译： 提供了晶片级封装以及用于生产具有防分层再分配层的晶片级封装的方法。 在一个实施例中，该方法包括在半导体管芯上建立内部再分布层。 内部再分布层包括含有金属布线特征的绝缘材料体。 在电介质材料的主体中形成无路由的介质块，并且不被金属布线特征中断。 外再分布层在内再分布层上产生并且包含金属平面，其被图案化以包括覆盖无路由介质块的一个或多个除气开口。 无路由介质块具有最小宽度，长度和深度，每个至少两倍于外再分布层的厚度。

公开(公告)号：US09281293B2

公开(公告)日：2016-03-08

申请号：US14067809

申请日：2013-10-30

申请人： Alan J. Magnus ,  Trung Q. Duong ,  Zhiwei Gong ,  Scott M. Hayes ,  Douglas G. Mitchell ,  Michael B. Vincent ,  Jason R. Wright ,  Weng F. Yap

发明人： Alan J. Magnus ,  Trung Q. Duong ,  Zhiwei Gong ,  Scott M. Hayes ,  Douglas G. Mitchell ,  Michael B. Vincent ,  Jason R. Wright ,  Weng F. Yap

IPC分类号： H01L23/00 ,  H01L21/56

CPC分类号： H01L24/97 ,  H01L21/568 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/19

摘要： Microelectronic packages having layered interconnect structures are provided, as are methods for the fabrication thereof. In one embodiment, the method includes forming a first plurality of interconnect lines in ohmic contact with a first bond pad row provided on a semiconductor. A dielectric layer is deposited over the first plurality of interconnect lines, the first bond pad row, and a second bond pad row adjacent the first bond pad row. A trench via is then formed in the dielectric layer to expose at least the second bond pad row therethrough. A second plurality of interconnect lines is formed in ohmic contact with the second bond pad row within the trench via. The second plurality of interconnect lines extends over the first bond pad row and is electrically isolated therefrom by the dielectric layer to produce at least a portion of the layered interconnect structure.

摘要翻译： 提供具有分层互连结构的微电子封装，以及制造它们的方法。 在一个实施例中，该方法包括形成与设置在半导体上的第一接合焊盘排欧姆接触的第一多个互连线。 介电层沉积在第一多个互连线上，第一接合焊盘行和与第一接合焊盘行相邻的第二接合焊盘排。 然后在电介质层中形成沟槽通孔，以至少暴露第二接合焊盘排。 第二多个互连线形成为与沟槽通孔内的第二接合焊盘排欧姆接触。 所述第二多个互连线延伸穿过所述第一接合焊盘行并且通过所述电介质层与其电隔离以产生所述分层互连结构的至少一部分。

公开(公告)号：US09040387B2

公开(公告)日：2015-05-26

申请号：US13591969

申请日：2012-08-22

申请人： Zhiwei Gong ,  Michael B Vincent ,  Scott M Hayes ,  Jason R Wright

发明人： Zhiwei Gong ,  Michael B Vincent ,  Scott M Hayes ,  Jason R Wright

IPC分类号： H01L21/30 ,  H01L23/538 ,  H01L21/78 ,  H01L23/48 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L25/10 ,  H01L23/00

摘要： Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging microelectronic device panels in a panel stack. Each microelectronic device panel includes a plurality of microelectronic devices and a plurality of package edge conductors extending therefrom. Trenches are formed in the panel stack exposing the plurality of package edge conductors. An electrically-conductive material is deposited into the trenches and contacts the plurality of package edge conductors exposed therethrough. The panel stack is then separated into partially-completed stacked microelectronic packages. For at least one of the partially-completed stacked microelectronic packages, selected portions of the electrically-conductive material are removed to define a plurality of patterned sidewall conductors interconnecting the microelectronic devices included within the stacked microelectronic package.

公开(公告)号：US09036363B2

公开(公告)日：2015-05-19

申请号：US14042623

申请日：2013-09-30

申请人： Michael B. Vincent ,  Zhiwei Gong

发明人： Michael B. Vincent ,  Zhiwei Gong

IPC分类号： H05K7/00 ,  H05K1/11 ,  H05K1/18 ,  H05K3/10 ,  H05K3/32

CPC分类号： H01L23/3114 ,  H01L23/49805 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2225/1076 ,  H01L2924/12042 ,  H01L2924/1815 ,  Y10T29/4913 ,  H01L2924/00

摘要： Embodiments of devices and methods of their manufacture include coupling first and second package surface conductors to a package surface with an intra-conductor insulating structure between the package surface conductors. The package surface conductors extend between and electrically couple sets of pads that are exposed at the package surface. Elongated portions of the package surface conductors are parallel with and adjacent to each other. The intra-conductor insulating structure is coupled between the package surface conductors along an entirety of the parallel and adjacent elongated portions, and the intra-conductor insulating structure electrically insulates the elongated portions of the package surface conductors from each other. Some embodiments may be implemented in conjunction with a stacked microelectronic package that includes sidewall conductors and an intra-conductor insulating structure between and electrically insulating the sidewall conductors from each other.

摘要翻译： 装置及其制造方法的实施例包括将第一和第二封装表面导体耦合到封装表面，并在封装表面导体之间具有导体内绝缘结构。 封装表面导体在封装表面露出的焊垫组之间延伸并电耦合。 包装表面导体的细长部分彼此平行并相邻。 导体内绝缘结构沿着整个平行和相邻的细长部分耦合在封装表面导体之间，并且导体内绝缘结构将封装表面导体的细长部分彼此电绝缘。 一些实施例可以结合堆叠的微电子封装来实现，该堆叠式微电子封装包括侧壁导体和导体间绝缘结构，并且使侧壁导体彼此电绝缘。

公开(公告)号：US09673150B2

公开(公告)日：2017-06-06

申请号：US14571878

申请日：2014-12-16

申请人： Zhiwei Gong ,  Scott M. Hayes ,  Michael B. Vincent

发明人： Zhiwei Gong ,  Scott M. Hayes ,  Michael B. Vincent

IPC分类号： H01L23/34 ,  H01L23/552 ,  H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L21/3205 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L23/552 ,  H01L21/3205 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49827 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05554 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/207 ,  H01L2924/3025 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015

摘要： An encapsulated semiconductor device package with an overlying conductive EMI or RFI shield in contact with an end of a grounded conductive component at a lateral side of the package, and methods of making the semiconductor device package.

公开(公告)号：US20160172309A1

公开(公告)日：2016-06-16

申请号：US14571878

申请日：2014-12-16

申请人： Zhiwei Gong ,  Scott M. Hayes ,  Michael B. Vincent

发明人： Zhiwei Gong ,  Scott M. Hayes ,  Michael B. Vincent

IPC分类号： H01L23/552 ,  H01L23/00 ,  H01L21/3205 ,  H01L21/56 ,  H01L21/78 ,  H01L23/495 ,  H01L23/31

CPC分类号： H01L23/552 ,  H01L21/3205 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49827 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05554 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/207 ,  H01L2924/3025 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015

摘要： An encapsulated semiconductor device package with an overlying conductive EMI or RFI shield in contact with an end of a grounded conductive component at a lateral side of the package, and methods of making the semiconductor device package.

摘要翻译： 一种封装的半导体器件封装，其具有与封装的侧面处的接地导电部件的端部接触的上覆导电EMI或RFI屏蔽以及制造半导体器件封装的方法。