公开(公告)号：US08878870B1

公开(公告)日：2014-11-04

申请号：US12533554

申请日：2009-07-31

Applicant: Satish Kumar Vutukuri ,  Haohong Wang ,  Li Sha ,  Tao Xie ,  Ching-Han Tsai ,  Tzun-Wei Lee ,  Leung Chung Lai ,  Shuhua Xiang

Inventor： Satish Kumar Vutukuri ,  Haohong Wang ,  Li Sha ,  Tao Xie ,  Ching-Han Tsai ,  Tzun-Wei Lee ,  Leung Chung Lai ,  Shuhua Xiang

IPC: G09G5/00 ,  G09G5/377 ,  G06T3/40 ,  G06T15/00 ,  G06T15/40 ,  G06T15/50

CPC classification number: G09G5/377 ,  G06F3/14 ,  G09G5/14 ,  G09G2310/0229 ,  G09G2340/125 ,  G09G2350/00

Abstract: Embodiments of the present invention provide graphic processing techniques and configurations including an apparatus comprising a storage medium having stored therein a table comprising information about respective positions and sizes of a number of rectangular blocks, the rectangular blocks to substantially form at least one plane having an arbitrary shape object, and at least one overlay engine operatively coupled with the table and associated with the at least one plane to request the information about the respective positions and the sizes of the number of rectangular blocks to provide graphics overlay of the arbitrary shape object. Other embodiments may be described and/or claimed.

Abstract translation: 本发明的实施例提供了图形处理技术和配置，其包括包括存储介质的设备，其中存储有包括关于多个矩形块的相应位置和大小的信息的表格，矩形块基本上形成至少一个具有任意 以及至少一个覆盖引擎，其可操作地与所述工作台耦合并与所述至少一个平面相关联，以请求关于矩形块的数量的相应位置和尺寸的信息以提供所述任意形状对象的图形叠加。 可以描述和/或要求保护其他实施例。

公开(公告)号：US08363729B1

公开(公告)日：2013-01-29

申请号：US12612836

申请日：2009-11-05

Applicant: Li Sha ,  Haohong Wang ,  Leung Chung Lai ,  Tzun Wei Lee

Inventor： Li Sha ,  Haohong Wang ,  Leung Chung Lai ,  Tzun Wei Lee

IPC: H04N7/26

CPC classification number: H04N19/18 ,  H04N19/1887 ,  H04N19/436 ,  H04N19/60 ,  H04N19/91

Abstract: Methods and systems for using a video data compression algorithm with parallel processing capability are provided. AC and DC coefficients associated with blocks of the video data, along with quantization errors, may be encoded using a variable length code. The quantization errors may be encoded using a scheme that assigns priorities to the quantization errors based on the position of their associated AC and/or DC coefficients in a block of the video data. The quantization errors may be appended to a bitstream in an order based on these priorities that enables parallel coding of the quantization errors and AC and DC coefficients in each block of video data. Data packing schemes may also be applied to the coded data to maximize the use of bandwidth resources in encoding and/or decoding.

公开(公告)号：US09135006B1

公开(公告)日：2015-09-15

申请号：US13603958

申请日：2012-09-05

Applicant: Li Sha ,  Ching-Han Tsai ,  Chi-Kuang Chen ,  Tzun-Wei Lee

Inventor： Li Sha ,  Ching-Han Tsai ,  Chi-Kuang Chen ,  Tzun-Wei Lee

IPC: G06F9/32 ,  G06F9/30

CPC classification number: G06F9/30058 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3806

Abstract: In accordance with the teachings described herein, systems and methods are provided for advanced execution of branch instructions in a microprocessor pipeline. In one embodiment, a branch instruction of an assembly language program code is executed that includes (i) a condition operand, (ii) a branch destination operand, and (iii) a program count operand. It is determined whether a current program count matches a stored program count operand. After determining that a condition was met when the branch instruction was executed, and in response to determining that the current program count matches the stored program count operand, a destination instruction specified by the stored branch destination operand is fetched.

Abstract translation: 根据本文所述的教导，提供了用于在微处理器管线中高级执行分支指令的系统和方法。 在一个实施例中，执行汇编语言程序代码的分支指令，其包括（i）条件操作数，（ii）分支目的地操作数和（iii）程序计数操作数。 确定当前程序计数是否与存储的程序计数操作数相匹配。 在确定在执行分支指令时满足条件之后，并且响应于确定当前程序计数与存储的程序计数操作数相匹配，获取由存储的分支目的地操作数指定的目的地指令。

公开(公告)号：US08275978B1

公开(公告)日：2012-09-25

申请号：US12504080

申请日：2009-07-16

Applicant: Li Sha ,  Ching-Han Tsai ,  Chi-Kuang Chen ,  Tzun-Wei Lee

Inventor： Li Sha ,  Ching-Han Tsai ,  Chi-Kuang Chen ,  Tzun-Wei Lee

IPC: G06F9/38

CPC classification number: G06F9/30058 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/322 ,  G06F9/324 ,  G06F9/3806

Abstract: In one embodiment the present invention includes a microprocessor that has a pipeline circuit, a branch circuit, and a control circuit. The pipeline circuit pipelines instructions for the microprocessor. The branch circuit is coupled to the pipeline circuit and operates to store branch information. The control circuit is coupled to the pipeline circuit and the branch circuit. The control circuit stores a first branch information from the pipeline circuit to the branch circuit when a first condition is met. The control circuit retrieves a second branch information from the branch stack circuit to the pipeline circuit when a second condition is met. In this manner, the need for dedicated pipeline flush circuitry is avoided.

Abstract translation: 在一个实施例中，本发明包括具有流水线电路，分支电路和控制电路的微处理器。 管道电路管道指令为微处理器。 分支电路耦合到流水线电路并操作以存储分支信息。 控制电路耦合到流水线电路和分支电路。 当满足第一条件时，控制电路将来自流水线电路的第一分支信息存储到分支电路。 当满足第二条件时，控制电路从分支堆栈电路检索第二分支信息到流水线电路。 以这种方式，避免了专用管道冲洗电路的需要。

公开(公告)号：US07982641B1

公开(公告)日：2011-07-19

申请号：US12613830

申请日：2009-11-06

Applicant: Guan-Ming Su ,  Leung Chung Lai ,  Wenchi Hsu ,  Qian Tang ,  Li Sha ,  Ching-Han Tsai

Inventor： Guan-Ming Su ,  Leung Chung Lai ,  Wenchi Hsu ,  Qian Tang ,  Li Sha ,  Ching-Han Tsai

IPC: H03M7/00

CPC classification number: H03M7/4006 ,  H04N19/13 ,  H04N19/61

Abstract: A system including a binarization module, an encoding module, and a prediction module. The binarization module is configured to binarize a syntax element and to generate symbols. The encoding module is configured to encode the symbols using context-adaptive binary arithmetic coding (CABAC). The prediction module is configured to generate a prediction for a number of renormalizations to be performed to renormalize an interval range when encoding one of the symbols. The encoding module encodes a next symbol following the one of the symbols based on the prediction before renormalization of the interval range is actually completed.

Abstract translation: 一种包括二值化模块，编码模块和预测模块的系统。 二值化模块被配置为二进制化语法元素并生成符号。 编码模块被配置为使用上下文自适应二进制算术编码（CABAC）对符号进行编码。 预测模块被配置为生成对要执行的多个重新归一化的预测，以便在对符号之一进行编码时对间隔范围进行重新归一化。 编码模块基于在实际完成间隔范围的重新归一化之前的预测，对符号之一之后的下一个符号进行编码。

公开(公告)号：US08711019B1

公开(公告)日：2014-04-29

申请号：US13185354

申请日：2011-07-18

Applicant: Guan-Ming Su ,  Leung Chung Lai ,  Wenchi Hsu ,  Qian Tang ,  Li Sha ,  Ching-Han Tsai

Inventor： Guan-Ming Su ,  Leung Chung Lai ,  Wenchi Hsu ,  Qian Tang ,  Li Sha ,  Ching-Han Tsai

IPC: H03M7/00

CPC classification number: H03M7/4006 ,  H04N19/13 ,  H04N19/61

Abstract: A system including a binarization module, a prediction module, and a shifting module. The encoding module is configured to encode symbols using context-adaptive binary arithmetic coding, in which the symbols are generated by binarizing a syntax element. The prediction module is configured to generate a prediction for a number of renormalizations to be performed to renormalize an interval range when encoding one of the symbols. The shifting module is configured to generate a renormalized interval range by shifting the binarized syntax element R times, where R is a number of leading zeros before a 1 in the binarized syntax element. The encoding module is configured to encode a next symbol following the one of the symbols based on the renormalized interval range.

Abstract translation: 一种包括二值化模块，预测模块和移位模块的系统。 编码模块被配置为使用上下文自适应二进制算术编码对符号进行编码，其中通过二元化语法元素来生成符号。 预测模块被配置为生成对要执行的多个重新归一化的预测，以便在对符号之一进行编码时对间隔范围进行重新归一化。 移位模块被配置为通过移位二进制化的语法元素R times来生成重新归一化的间隔范围，其中R是二进制化语法元素中的1之前的前导零的数量。 编码模块被配置为基于重新归一化的间隔范围对符号之后的下一个符号进行编码。

公开(公告)号：US08363969B1

公开(公告)日：2013-01-29

申请号：US12534632

申请日：2009-08-03

Applicant: Haohong Wang ,  Li Sha

Inventor： Haohong Wang ,  Li Sha

IPC: G06K9/36

CPC classification number: H04N19/423 ,  H04N19/12 ,  H04N19/126 ,  H04N19/13 ,  H04N19/15 ,  H04N19/18 ,  H04N19/184 ,  H04N19/30

Abstract: Embodiments of the present invention include systems and methods for processing and coding image data. In one embodiment, image data is coded using a first image coding process. If a bit rate constraint is satisfied, the image data is output. If the bit rate constraint is not satisfied, the image data is coded using a second different coding process. In one embodiment, the second coding process is a layered coding process. In another embodiment, if the constraint is satisfied, quantization data may be included in the output, and may be coded using layered coding. Variable length coding processes and hardware implementations are further disclosed for efficient image processing.

Abstract translation: 本发明的实施例包括用于处理和编码图像数据的系统和方法。 在一个实施例中，使用第一图像编码处理对图像数据进行编码。 如果满足比特率约束，则输出图像数据。 如果不满足比特率约束，则使用第二不同的编码处理对图像数据进行编码。 在一个实施例中，第二编码处理是分层编码处理。 在另一个实施例中，如果约束被满足，量化数据可以被包括在输出中，并且可以使用分层编码进行编码。 进一步公开了可变长度编码处理和硬件实现用于有效的图像处理。

公开(公告)号：US08587609B1

公开(公告)日：2013-11-19

申请号：US12510834

申请日：2009-07-28

Applicant: Haohong Wang ,  Yunsen Chin ,  Li Sha ,  Shuhua Xiang

Inventor： Haohong Wang ,  Yunsen Chin ,  Li Sha ,  Shuhua Xiang

IPC: G09G5/00 ,  G09G5/24 ,  G06T11/00

CPC classification number: G06T11/40 ,  G06T11/203 ,  G09G5/246 ,  G09G5/28

Abstract: Embodiments of the present invention provide methods and associated architecture of accuracy adaptive and scalable vector graphics rendering including rendering a graphic comprising a plurality of line segments by processing each of the plurality of line segments in a first pass, and processing each of a plurality of pixels through which the plurality of line segments pass in a second pass, automatically detecting one or more rendering errors of the graphic, and correcting the one or more rendering errors. Other embodiments may be described and/or claimed.

Abstract translation: 本发明的实施例提供了精度自适应和可缩放的矢量图形渲染的方法和相关架构，包括通过在第一遍中处理多个线段中的每一个来渲染包括多个线段的图形，以及处理多个像素 多个线段通过其通过第二遍，自动检测图形的一个或多个渲染错误，以及校正一个或多个渲染错误。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20050228970A1

公开(公告)日：2005-10-13

申请号：US10209109

申请日：2002-07-30

Applicant: Shuhua Xiang ,  Li Sha ,  Ping Zhu ,  Hongjun Yuan ,  Wei Ni

Inventor： Shuhua Xiang ,  Li Sha ,  Ping Zhu ,  Hongjun Yuan ,  Wei Ni

IPC: G06F7/57 ,  G06F9/38 ,  G06F15/00

CPC classification number: G06F9/3867 ,  G06F7/57 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3885

Abstract: A processing system includes an arithmetic logic unit (ALU) sub-system that allows data associated with a prior instruction to be preserved for use with a next instruction or subsequent instruction without having to reload the value using an intermediate register. The ALU sub-system includes a pair of ALUs communicatively cross-coupled with a pair of accumulators. The processing system also includes a data selector coupled to the ALU sub-system for use with memory contention prediction. The data selector includes a constant generator that controls storage of data associated with a previous instruction in a bypass element, and a selector to choose between data from a databus element and data stored in the bypass element.

Abstract translation: 处理系统包括算术逻辑单元（ALU）子系统，其允许与先前指令相关联的数据被保留以用于下一个指令或后续指令，而不必使用中间寄存器重新加载该值。 ALU子系统包括与一对蓄能器通信地交叉耦合的一对ALU。 处理系统还包括耦合到ALU子系统以与存储器争用预测一起使用的数据选择器。 数据选择器包括恒定发生器，其控制与旁路元件中的先前指令相关联的数据的存储，以及选择器，用于在数据总线元件的数据和存储在旁路元件中的数据之间进行选择。

公开(公告)号：US20050213661A1

公开(公告)日：2005-09-29

申请号：US09924079

申请日：2001-08-07

Applicant: Shuhua Xiang ,  Li Sha ,  Yaojun Luo

Inventor： Shuhua Xiang ,  Li Sha ,  Yaojun Luo

IPC: G06T7/20 ,  H04N5/14 ,  H04N7/12 ,  H04N7/18 ,  H04N7/26

CPC classification number: H04N19/523 ,  G06T7/223 ,  G06T2207/10016 ,  H04N5/145 ,  H04N19/43 ,  H04N19/53

Abstract: A method, apparatus, computer medium, and other embodiments for motion estimation and compensation processing of video and image signals are described. Within a sequence of frames, block-based differences are taken between frames to exploit redundancies between pictures by taking a matchblock from the current picture and by determining a spatial offset in a corresponding reference picture which signifies a good prediction of where the current macroblock can be found. Multi-level motion estimation is performed in three stages to refine the resolution of the motion vector with reduced computational bandwidth. First, a matchblock from a reference frame is decomposed equally into several sub-matchblocks, each of which is searched in parallel over a search area decomposed into sub-blocks by a similar factor so as to determine a preliminary motion vector in the reference picture. Second, a full size matchblock is then searched over a refined search area using the preliminary motion vector to determine an intermediate motion vector, so as to refine the resolution of the preliminary motion vector. Third, fractional-pixel searching is then performed on the matchblock and the intermediate motion vector to determine a final motion vector having an even higher resolution associated with the best motion vector to be used in predicting the current macroblock. In one embodiment, a processor-based motion estimation and compensation cell array enables contemporaneous and independent loading and processing operations in parallel.

Abstract translation: 描述了用于视频和图像信号的运动估计和补偿处理的方法，装置，计算机介质和其它实施例。 在一系列帧内，在帧之间采用基于块的差异，以通过从当前图像获取匹配块并且通过确定相应参考图片中的空间偏移来表示图像之间的冗余，其表示对当前宏块可以在何处的良好预测 发现。 多级运动估计分三个阶段进行，以减少计算带宽的细化运动矢量的分辨率。 首先，来自参考帧的匹配块被分解为几个子匹配块，每个子块通过相似的因素并行地搜索到被分解成子块的搜索区域，以便确定参考图片中的初步运动矢量。 其次，使用初步运动向量，在精细搜索区域上搜索全尺寸匹配块，以确定中间运动矢量，以便精细化预备运动矢量的分辨率。 第三，然后对匹配块和中间运动矢量执行分数像素搜索，以确定具有与用于预测当前宏块的最佳运动矢量相关联的更高分辨率的最终运动矢量。 在一个实施例中，基于处理器的运动估计和补偿单元阵列能够并行地实现同时且独立的加载和处理操作。