公开(公告)号：US20050076181A1

公开(公告)日：2005-04-07

申请号：US10711792

申请日：2004-10-06

Applicant: Wenchi Hsu

Inventor： Wenchi Hsu

IPC: G06F12/08 ,  G06F12/00

CPC classification number: G06F12/0862

Abstract: The present invention provides a pre-fetch controller and a method thereof for efficiently pre-fetching data from a memory device. The method includes initializing a counter value; fetching a data from the memory and subtracting the counter value by a first value when a pre-fetching is activated; adding a second value to the counter value when a cache hit occurs; comparing the counter value with a first threshold value; and when the counter value is smaller than the first threshold value, stopping pre-fetching the data from the memory.

Abstract translation: 本发明提供了一种用于从存储器件有效地预取数据的预取控制器及其方法。 该方法包括初始化计数器值; 当预取被激活时，从存储器取出数据并减去计数器值第一值; 当缓存命中发生时，向计数器值添加第二个值; 将所述计数器值与第一阈值进行比较; 并且当计数器值小于第一阈值时，停止从存储器预取数据。

公开(公告)号：US08711019B1

公开(公告)日：2014-04-29

申请号：US13185354

申请日：2011-07-18

Applicant: Guan-Ming Su ,  Leung Chung Lai ,  Wenchi Hsu ,  Qian Tang ,  Li Sha ,  Ching-Han Tsai

Inventor： Guan-Ming Su ,  Leung Chung Lai ,  Wenchi Hsu ,  Qian Tang ,  Li Sha ,  Ching-Han Tsai

IPC: H03M7/00

CPC classification number: H03M7/4006 ,  H04N19/13 ,  H04N19/61

Abstract: A system including a binarization module, a prediction module, and a shifting module. The encoding module is configured to encode symbols using context-adaptive binary arithmetic coding, in which the symbols are generated by binarizing a syntax element. The prediction module is configured to generate a prediction for a number of renormalizations to be performed to renormalize an interval range when encoding one of the symbols. The shifting module is configured to generate a renormalized interval range by shifting the binarized syntax element R times, where R is a number of leading zeros before a 1 in the binarized syntax element. The encoding module is configured to encode a next symbol following the one of the symbols based on the renormalized interval range.

Abstract translation: 一种包括二值化模块，预测模块和移位模块的系统。 编码模块被配置为使用上下文自适应二进制算术编码对符号进行编码，其中通过二元化语法元素来生成符号。 预测模块被配置为生成对要执行的多个重新归一化的预测，以便在对符号之一进行编码时对间隔范围进行重新归一化。 移位模块被配置为通过移位二进制化的语法元素R times来生成重新归一化的间隔范围，其中R是二进制化语法元素中的1之前的前导零的数量。 编码模块被配置为基于重新归一化的间隔范围对符号之后的下一个符号进行编码。

公开(公告)号：US20080046659A1

公开(公告)日：2008-02-21

申请号：US11851382

申请日：2007-09-06

Applicant: Wenchi Hsu

Inventor： Wenchi Hsu

IPC: G06F12/00

CPC classification number: G06F12/0862

Abstract: A pre-fetch controller for pre-fetching data from a memory and providing data to a logic operation unit is disclosed. The pre-fetch controller includes a register for storing a counter value and a controller connected to the register for changing the counter value when a pre-fetching is activated and for changing the counter value when a cache hit occurs.

Abstract translation: 公开了一种用于从存储器预取数据并向逻辑运算单元提供数据的预取控制器。 预取控制器包括用于存储计数器值的寄存器和连接到寄存器的控制器，用于当预取被激活时改变计数器值，并且当发生高速缓存命中时改变计数器值。

公开(公告)号：US08108615B2

公开(公告)日：2012-01-31

申请号：US11851382

申请日：2007-09-06

Applicant: Wenchi Hsu

Inventor： Wenchi Hsu

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F12/0862

Abstract: A pre-fetch controller for pre-fetching data from a memory and providing data to a logic operation unit is disclosed. The pre-fetch controller includes a register for storing a counter value and a controller connected to the register for changing the counter value when a pre-fetching is activated and for changing the counter value when a cache hit occurs.

Abstract translation: 公开了一种用于从存储器预取数据并向逻辑运算单元提供数据的预取控制器。 预取控制器包括用于存储计数器值的寄存器和连接到寄存器的控制器，用于当预取被激活时改变计数器值，并且当发生高速缓存命中时改变计数器值。

公开(公告)号：US07313655B2

公开(公告)日：2007-12-25

申请号：US10711792

申请日：2004-10-06

Applicant: Wenchi Hsu

Inventor： Wenchi Hsu

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F12/0862

Abstract: The present invention provides a pre-fetch controller and a method thereof for efficiently pre-fetching data from a memory device. The method includes initializing a counter value; fetching a data from the memory and subtracting the counter value by a first value when a pre-fetching is activated; adding a second value to the counter value when a cache hit occurs; comparing the counter value with a first threshold value; and when the counter value is smaller than the first threshold value, stopping pre-fetching the data from the memory.

Abstract translation: 本发明提供了一种用于从存储器件有效地预取数据的预取控制器及其方法。 该方法包括初始化计数器值; 当预取被激活时，从存储器取出数据并减去计数器值第一值; 当缓存命中发生时，向计数器值添加第二个值; 将所述计数器值与第一阈值进行比较; 并且当计数器值小于第一阈值时，停止从存储器预取数据。

公开(公告)号：US07982641B1

公开(公告)日：2011-07-19

申请号：US12613830

申请日：2009-11-06

Applicant: Guan-Ming Su ,  Leung Chung Lai ,  Wenchi Hsu ,  Qian Tang ,  Li Sha ,  Ching-Han Tsai

Inventor： Guan-Ming Su ,  Leung Chung Lai ,  Wenchi Hsu ,  Qian Tang ,  Li Sha ,  Ching-Han Tsai

IPC: H03M7/00

CPC classification number: H03M7/4006 ,  H04N19/13 ,  H04N19/61

Abstract: A system including a binarization module, an encoding module, and a prediction module. The binarization module is configured to binarize a syntax element and to generate symbols. The encoding module is configured to encode the symbols using context-adaptive binary arithmetic coding (CABAC). The prediction module is configured to generate a prediction for a number of renormalizations to be performed to renormalize an interval range when encoding one of the symbols. The encoding module encodes a next symbol following the one of the symbols based on the prediction before renormalization of the interval range is actually completed.

Abstract translation: 一种包括二值化模块，编码模块和预测模块的系统。 二值化模块被配置为二进制化语法元素并生成符号。 编码模块被配置为使用上下文自适应二进制算术编码（CABAC）对符号进行编码。 预测模块被配置为生成对要执行的多个重新归一化的预测，以便在对符号之一进行编码时对间隔范围进行重新归一化。 编码模块基于在实际完成间隔范围的重新归一化之前的预测，对符号之一之后的下一个符号进行编码。