公开(公告)号：US09299409B2

公开(公告)日：2016-03-29

申请号：US14201642

申请日：2014-03-07

申请人： Tadashi Miyakawa ,  Katsuhiko Hoya ,  Mariko Ilzuka ,  Takashi Nakazawa ,  Hiroyuki Takenaka

发明人： Tadashi Miyakawa ,  Katsuhiko Hoya ,  Mariko Ilzuka ,  Takashi Nakazawa ,  Hiroyuki Takenaka

IPC分类号： G11C11/00 ,  G11C11/16 ,  G11C7/12 ,  G11C13/00

CPC分类号： H01L27/228 ,  G11C7/12 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0002 ,  H01L43/08

摘要： According to one embodiment, a semiconductor storage device includes a cell array including resistance change elements formed above a semiconductor substrate; first cell transistors formed on the semiconductor substrate and provided in association with the resistance change elements; first gate electrodes included in the first cell transistor and extending in a first direction; a first bit lines electrically connected to the resistance change elements respectively and extending in a second direction perpendicular to the first direction; a second bit lines electrically connected to one end of a current path of the first cell transistors respectively and extending in the second direction; and first active areas in which the first cell transistors are formed, and which extend in a direction crossing the first direction at a first angle.

摘要翻译： 根据一个实施例，半导体存储装置包括：单元阵列，其包括形成在半导体衬底上方的电阻变化元件; 形成在半导体衬底上并与电阻变化元件相关联地设置的第一单元晶体管; 包括在第一单元晶体管中并沿第一方向延伸的第一栅电极; 分别电连接到所述电阻变化元件并沿垂直于所述第一方向的第二方向延伸的第一位线; 第二位线分别电连接到第一单元晶体管的电流路径的一端并沿第二方向延伸; 以及第一有源区，其中形成有第一单元晶体管，并且在与第一方向交叉的方向上以第一角度延伸。

公开(公告)号：US09025400B2

公开(公告)日：2015-05-05

申请号：US13601037

申请日：2012-08-31

申请人： Katsuyuki Fujita ,  Katsuhiko Hoya

发明人： Katsuyuki Fujita ,  Katsuhiko Hoya

IPC分类号： G11C11/16 ,  G11C8/18 ,  G11C7/22

CPC分类号： G11C11/1693 ,  G11C7/222 ,  G11C8/18 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1673

摘要： A semiconductor storage device according to the present embodiment includes a plurality of memory units respectively comprising a plurality of memory cells. A data bus is shared by the memory units and transfers data from the memory units or to the memory units. A timing controller includes a delay time unit shared by the memory units sharing the data bus. The timing controller is configured to output a control signal for driving the memory units after a predetermined delay time elapses since receiving an input signal.

摘要翻译： 根据本实施例的半导体存储装置包括分别包括多个存储单元的多个存储单元。 数据总线由存储器单元共享并从存储器单元或存储器单元传送数据。 定时控制器包括由共享数据总线的存储器单元共享的延迟时间单元。 定时控制器被配置为在接收到输入信号之后经过预定的延迟时间之后输出用于驱动存储器单元的控制信号。

公开(公告)号：US08654596B2

公开(公告)日：2014-02-18

申请号：US13604338

申请日：2012-09-05

申请人： Katsuhiko Hoya

发明人： Katsuhiko Hoya

IPC分类号： G11C7/10

CPC分类号： G11C7/1006 ,  G11C11/16 ,  G11C13/00

摘要： A semiconductor storage device includes plural bit lines and plural word lines. The memory cell array has plural memory cells that are connected with the bit lines and word lines, and can store data. Plural sense amplifiers detect the data stored in the memory cells. Plural write drivers write data in the memory cells. A comparison buffer temporarily stores the write data to be written in the memory cells by the write driver. In a series of write sequences, the comparison buffer stores the read data from the memory cells selected as the write object and the write data to be written in the selected memory cells. After a series of write sequences, when the pre-charge command for resetting the voltage of the bit lines is received, the write execution command is executed so that the comparison buffer executes write in the selected memory cells.

摘要翻译： 半导体存储装置包括多个位线和多个字线。 存储单元阵列具有与位线和字线连接的多个存储单元，并且可以存储数据。 多个读出放大器检测存储在存储单元中的数据。 多个写入驱动程序将数据写入存储单元。 比较缓冲器通过写驱动器临时存储要写入存储单元的写数据。 在一系列写入序列中，比较缓冲器存储来自被选择作为写入对象的存储器单元的读取数据和要写入所选存储单元的写入数据。 在一系列写入序列之后，当接收到用于重置位线的电压的预充电命令时，执行写入执行命令，使得比较缓冲器在所选存储单元中执行写入。

公开(公告)号：US07729157B2

公开(公告)日：2010-06-01

申请号：US12201328

申请日：2008-08-29

申请人： Katsuhiko Hoya

发明人： Katsuhiko Hoya

IPC分类号： G11C11/12 ,  G11C11/24 ,  G11C29/00 ,  G11C7/00

CPC分类号： G11C11/22 ,  G06F11/1008 ,  G11C2029/0411

摘要： A memory cell array has memory cells, each of which has a ferroelectric capacitor and a selection transistor. A plate line is connected to one end of the ferroelectric capacitor and applied a certain plate line voltage. A sense amplifier circuit senses and amplifies voltage of the bit line. An error correction circuit corrects any error in retained data in the memory cells sensed by the sense amplifier. A plate line control circuit controls the timing for switching a potential of the plate line to a ground potential, based on absence or presence of error correction by the error correction circuit.

摘要翻译： 存储单元阵列具有存储单元，每个存储单元具有铁电电容器和选择晶体管。 板线连接到铁电电容器的一端并施加一定的板线电压。 读出放大器电路感测并放大位线的电压。 误差校正电路校正由读出放大器感测到的存储单元中的保留数据中的任何错误。 基于错误校正电路的错误校正的不存在或存在，板线控制电路控制将板线的电位切换到接地电位的定时。

公开(公告)号：US20060280023A1

公开(公告)日：2006-12-14

申请号：US11440110

申请日：2006-05-25

申请人： Katsuhiko Hoya ,  Tohru Ozaki

发明人： Katsuhiko Hoya ,  Tohru Ozaki

IPC分类号： G11C8/00

CPC分类号： G11C11/22

摘要： A semiconductor memory device includes a row of memory cells connected in series, each of the memory cells including a ferroelectric capacitor and a cell transistor having a gate terminal and source/drain terminals, the source/drain terminals being connected in parallel with two electrodes of the ferroelectric capacitor, a word line connected to the gate terminal, memory cell blocks each including the row of memory cells and a block select transistor, a drain terminal of the block select transistor being connected to one end of the row of memory cells, a plate line connected to another end thereof, a bit line connected to a source terminal of the block select transistor, and a block select line connected to a gate terminal of the block select transistor, wherein a contact is provided under the plate line to connect the source terminal of the block select transistor and the bit line.

摘要翻译： 半导体存储器件包括串联连接的一行存储器单元，每个存储器单元包括铁电电容器和具有栅极端子和源极/漏极端子的单元晶体管，源极/漏极端子与两个电极 铁电电容器，连接到栅极端子的字线，每个包括行存储单元的存储单元块和块选择晶体管，块选择晶体管的漏极端子连接到该行存储单元的一端， 连接到其另一端的板线，连接到块选择晶体管的源极端的位线和连接到块选择晶体管的栅极端子的块选择线，其中在板线下方提供接触以将 块选择晶体管的源极端子和位线。

公开(公告)号：US08908446B2

公开(公告)日：2014-12-09

申请号：US13607689

申请日：2012-09-08

申请人： Akira Katayama ,  Katsuhiko Hoya

发明人： Akira Katayama ,  Katsuhiko Hoya

IPC分类号： G11C16/04 ,  G11C7/10

CPC分类号： G11C7/10 ,  G11C7/1012 ,  G11C7/1087 ,  G11C7/1093

摘要： A semiconductor device includes a first latch unit that latches write data based on a strobe signal, a second latch unit that receives the write data latched in the first latch unit based on a first clock signal, and a strobe generation unit that generates the strobe signal and supplies it to the first latch unit. The strobe generation unit includes a bit shift counter, which receives a second clock signal and outputs a bit shift signal having a logic level that is inverted every plural clock cycles of the second clock signal, and a logic gate that outputs the second clock signal as the strobe signal according to the bit shift signal. The latch period of the write data in the first latch part is determined by the period of the strobe signal and also the period of the bit shift signal.

摘要翻译： 半导体器件包括：第一锁存单元，其基于选通信号锁存写入数据;第二锁存单元，其基于第一时钟信号接收锁存在第一锁存单元中的写入数据;以及选通产生单元，其生成选通信号 并将其提供给第一锁存单元。 选通产生单元包括位移计数器，其接收第二时钟信号并输出​​具有在第二时钟信号的每多个时钟周期被反相的逻辑电平的位移信号，以及输出第二时钟信号的逻辑门作为 根据位移信号的选通信号。 第一锁存部分中写入数据的锁存周期由选通信号的周期以及位移信号的周期确定。

公开(公告)号：US08482969B2

公开(公告)日：2013-07-09

申请号：US13228255

申请日：2011-09-08

申请人： Katsuhiko Hoya ,  Kenji Tsuchida

发明人： Katsuhiko Hoya ,  Kenji Tsuchida

IPC分类号： G11C11/00

CPC分类号： G11C11/1693 ,  G11C11/1675

摘要： A memory according to an embodiment includes bit lines, word lines, source lines, magnetic tunnel junction elements and transistors that are serially connected between the bit lines and the source lines, respectively, and a sense amplifier that detects data stored in the magnetic tunnel junction elements. The semiconductor storage device includes multiplexers between the bit lines and the sense amplifier in order to select one of the bit lines to be connected to the sense amplifier, and write amplifiers that are located corresponding to memory cell blocks each of which includes memory cells each including the magnetic tunnel junction element and the transistor and are connected to the bit lines or connected via the multiplexers to the bit lines. To write data, the sense amplifier applies a write voltage to the bit lines and then the write amplifiers hold the write voltage.

摘要翻译： 根据实施例的存储器分别包括位线和源极线之间串联连接的位线，字线，源极线，磁性隧道结元件和晶体管，以及检测放大器，其检测存储在磁性隧道结中的数据 元素。 半导体存储装置包括位线和读出放大器之间的多路复用器，以便选择要连接到读出放大器的位线之一，以及对应于存储单元块的写入放大器，每个存储单元块包括各自包括 磁性隧道结元件和晶体管，并且连接到位线或经由多路复用器连接到位线。 为了写入数据，读出放大器向位线施加写入电压，然后写入放大器保持写入电压。

公开(公告)号：US20120243304A1

公开(公告)日：2012-09-27

申请号：US13421505

申请日：2012-03-15

申请人： Katsuhiko Hoya

发明人： Katsuhiko Hoya

IPC分类号： G11C11/16

CPC分类号： G11C11/1673 ,  G06F11/1048 ,  G11C7/1006 ,  G11C7/1096 ,  G11C8/14 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1677 ,  G11C11/1693 ,  G11C2029/0411 ,  G11C2211/5615

摘要： A semiconductor storage device according to the present embodiment comprises a plurality of bit lines, a plurality of word lines, and a plurality of memory cells corresponding to intersections between the bit lines and the word lines, respectively, and including magnetic tunnel junction elements capable of storing data. A plurality of sense amplifiers respectively correspond to the bit lines and are configured to detect data stored in the memory cells via a bit line selected from among the corresponding bit lines. A plurality of read latch parts correspond to the sense amplifiers, respectively, and are configured to latch data detected by the corresponding sense amplifiers. A plurality of read global data buses are connected to the read latch parts, respectively, and are configured to consecutively transmit data latched by the read latch parts at a time of a data read operation.

摘要翻译： 根据本实施例的半导体存储装置分别包括多个位线，多个字线和对应于位线和字线之间的交点的多个存储单元，并且包括能够 存储数据。 多个读出放大器分别对应于位线，并且被配置为经由从相应位线中选择的位线来检测存储在存储单元中的数据。 多个读取锁存部分别对应于读出放大器，并且被配置为锁存由对应的读出放大器检测到的数据。 多个读取全局数据总线分别连接到读取锁存器部分，并且被配置为在数据读取操作时连续发送由读取锁存器部件锁存的数据。

公开(公告)号：US20110158008A1

公开(公告)日：2011-06-30

申请号：US12883731

申请日：2010-09-16

申请人： Hisaaki NISHIMURA ,  Katsuhiko Hoya

发明人： Hisaaki NISHIMURA ,  Katsuhiko Hoya

IPC分类号： G11C7/00

CPC分类号： G11C7/1051 ,  G11C7/1012 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1069

摘要： According to one embodiment, in a semiconductor storage device, a first internal bus, a second internal bus, and a third internal bus have bus widths decreasing stepwise from a memory cell array side to a data output circuit side. A first selection circuit and a second selection circuit divide the data, which is input via the first or second internal bus, according to a rate of a decrease in bus width in an input and an output, time-divide the divided data, and output the divided data to the second or third internal bus.

摘要翻译： 根据一个实施例，在半导体存储装置中，第一内部总线，第二内部总线和第三内部总线具有从存储单元阵列侧到数据输出电路侧逐步减小的总线宽度。 第一选择电路和第二选择电路根据输入和输出中的总线宽度的减小率，将经由第一或第二内部总线输入的数据除以划分的数据，并输出 分配数据到第二或第三内部总线。

公开(公告)号：US07161202B2

公开(公告)日：2007-01-09

申请号：US10738999

申请日：2003-12-19

申请人： Katsuhiko Hoya ,  Daisaburo Takashima

发明人： Katsuhiko Hoya ,  Daisaburo Takashima

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/11507 ,  H01L21/76895 ,  H01L27/11502

摘要： First and second ferroelectric capacitors are selectively connected with a first bit line. Data is read to the first bit line from a first ferroelectric capacitor by applying a first voltage in a coordinate increasing direction of an axis or from the second ferroelectric capacitor by applying a second voltage having a sign opposite to the first voltage in the coordinate increasing direction. Third and fourth ferroelectric capacitors are selectively connected with a second bit line. Data is read to the second bit line from the third ferroelectric capacitor by applying a third voltage having the same sign as the first voltage in the coordinate increasing direction or from the fourth ferroelectric capacitor by applying a fourth voltage having the same sign as the second voltage in the coordinate increasing direction. A sense amplifier amplifies the potential difference between the first and second bit lines.

摘要翻译： 第一和第二铁电电容器选择性地与第一位线连接。 通过在坐标增加方向施加具有与第一电压相反的符号的第二电压，通过在轴的坐标增加方向上施加第一电压或从第二铁电电容器向第一位线读取数据到第一位线 。 第三和第四铁电电容器选择性地与第二位线连接。 通过施加具有与第二电压相同的符号的第四电压，通过施加具有与坐标增加方向上的第一电压相同的符号的第三电压或从第四铁电电容器向第二位线读取数据到第二位线 在坐标增加方向。 读出放大器放大第一和第二位线之间的电位差。