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    Techniques to mitigate asymmetric long delay stress
    1.
    发明授权
    Techniques to mitigate asymmetric long delay stress 有权

    公开(公告)号：US11900980B2

    公开(公告)日：2024-02-13

    申请号：US17690614

    申请日：2022-03-09

    Applicant: Micron Technology, Inc.

    Inventor： Angelo Visconti

    IPC: G11C11/12 ,  G11C11/22

    CPC classification number: G11C11/2259 ,  G11C11/221 ,  G11C11/2275

    Abstract: Methods, systems, and devices for techniques to mitigate asymmetric long delay stress are described. A memory device may activate a memory cell during a first phase of an access operation cycle. The memory device may write a first state or a second state to the memory cell during the first phase of the access operation cycle. The memory device may maintain the first state or the second state during a second phase of the access operation cycle after the first phase of the access operation cycle. The memory device may write, during a third phase of the access operation cycle after the second phase of the access operation cycle, the second state to the memory cell. The memory device may precharge the memory cell during the third phase of the access operation cycle based on writing the second state to the memory cell.

    METHOD AND MEDIA FOR IMPROVING FERROELECTRIC DOMAIN STABILITY IN AN INFORMATION STORAGE DEVICE
    3.
    发明申请
    METHOD AND MEDIA FOR IMPROVING FERROELECTRIC DOMAIN STABILITY IN AN INFORMATION STORAGE DEVICE 失效
    用于改善信息存储设备中的电磁域稳定性的方法和媒体

    公开(公告)号：US20090021975A1

    公开(公告)日：2009-01-22

    申请号：US11778571

    申请日：2007-07-16

    Applicant: Valluri Ramana Rao ,  Li-Peng Wang ,  Qing Ma ,  Byong Man Kim

    Inventor： Valluri Ramana Rao ,  Li-Peng Wang ,  Qing Ma ,  Byong Man Kim

    IPC: G11C11/12 ,  B32B15/04 ,  H01L21/62

    CPC classification number: G11B9/02 ,  Y10S977/947

    Abstract: A media for an information storage device comprises a substrate of single-crystal silicon, a buffer layer of an epitaxial single crystal insulator formed over the substrate, a bottom electrode layer of an epitaxial single crystal conductor formed over the buffer layer, a ferroelectric layer of an epitaxial single crystal ferroelectric material formed over the bottom electrode layer, and an overlayer of an epitaxial single crystal material formed over the ferroelectric layer. Dipole charges generally having a first orientation exist at an interface between the bottom electrode layer and the ferroelectric layer includes, while dipole charges generally having a second orientation opposite the first orientation exist at an interface between the ferroelectric layer and the overlayer includes.

    Abstract translation: 用于信息存储装置的介质包括单晶硅衬底，形成在衬底上的外延单晶绝缘体的缓冲层，形成在缓冲层上的外延单晶导体的底电极层，形成在缓冲层上的铁电层 形成在底部电极层上的外延单晶铁电材料，以及形成在铁电体层上的外延单晶材料的覆层。 通常具有第一取向的偶极电荷存在于底电极层和铁电层之间的界面处，其中通常具有与第一取向相反的第二取向的偶极电荷存在于铁电层和覆层之间的界面处。

    Self-adjusting reference current for a memory
    8.
    发明授权
    Self-adjusting reference current for a memory 有权

    公开(公告)号：US12183381B2

    公开(公告)日：2024-12-31

    申请号：US17659798

    申请日：2022-04-19

    Applicant: Ferroelectric Memory GmbH

    Inventor： Georgi Kuzmanov

    IPC: G11C11/12 ,  G11C11/22

    Abstract: Disclosed herein is a memory cell arrangement and method thereof for providing a reference read current for reading a plurality of memory cells. The memory cell arrangement includes a plurality of memory cells and one or more reference memory cells. The memory cell arrangement also includes a reference circuit that provides a reference read current for reading one or more of the plurality memory cells, wherein the reference circuit is connected to the one or more reference memory cells to generate the reference read current based on one or more reference currents from the one or more reference memory cells. The memory cell arrangement may also include a shifting circuit connected to the reference circuit, wherein the shifting circuit is configured to shift the reference read current.

    Time-based access of a memory cell
    9.
    发明授权
    Time-based access of a memory cell 有权

    公开(公告)号：US11264074B2

    公开(公告)日：2022-03-01

    申请号：US17354672

    申请日：2021-06-22

    Applicant: Micron Technology, Inc.

    Inventor： Umberto Di Vincenzo

    IPC: G11C11/12 ,  G11C11/22 ,  G11C11/56 ,  G11C11/00

    Abstract: Techniques, systems, and devices for time-resolved access of memory cells in a memory array are described herein. During a sense portion of a read operation, a selected memory cell may be charged to a predetermined voltage level. A logic state stored on the selected memory cell may be identified based on a duration between the beginning of the charging and when selected memory cell reaches the predetermined voltage level. In some examples, time-varying signals may be used to indicate the logic state based on the duration of the charging. In some examples, the duration of the charging may be based on a polarization state of the selected memory cell, a dielectric charge state of the selected state, or both a polarization state and a dielectric charge state of the selected memory cell.

    Semiconductor memory and test method for the semiconductor memory
    10.
    发明授权
    Semiconductor memory and test method for the semiconductor memory 失效
    半导体存储器的半导体存储器和测试方法

    公开(公告)号：US08248835B2

    公开(公告)日：2012-08-21

    申请号：US12718800

    申请日：2010-03-05

    Applicant: Tadashi Miyakawa ,  Daisaburo Takashima

    Inventor： Tadashi Miyakawa ,  Daisaburo Takashima

    IPC: G11C11/12

    CPC classification number: G11C29/50 ,  G11C11/22 ,  G11C29/12005 ,  G11C29/1201 ,  G11C2029/1204

    Abstract: Semiconductor memory contains memory cells having ferroelectric capacitors and cell transistors, bit lines connected to memory cells, word lines connected to gate electrodes of cell transistors, plate lines connected to one of two electrodes of ferroelectric capacitors, sense amplifiers connected between each pair of bit lines. Further, a test pad is provided in order to apply an external voltage to each of bit lines, test transistors are provided corresponding to bit lines respectively, each of test transistors is connected between the test pad and each of bit lines, a fatigue test bias circuit is connected to a first node located between the test pad and test transistors. Test transistors are shared in a first test to apply a first voltage to ferroelectric capacitors from an outside via the test pad and a second test to apply a second voltage to ferroelectric capacitors from the fatigue test bias circuit.

    Abstract translation: 半导体存储器包括具有铁电电容器和单元晶体管的存储单元，连接到存储单元的位线，连接到单元晶体管的栅电极的字线，连接到铁电电容器的两个电极之一的板线，连接在每对位线之间的读出放大器 。 此外，为了对每个位线施加外部电压，提供了测试焊盘，分别对应于位线提供了测试晶体管，每个测试晶体管连接在测试焊盘和每个位线之间，疲劳测试偏置 电路连接到位于测试焊盘和测试晶体管之间的第一节点。 测试晶体管在第一测试中被共享，以通过测试焊盘从外部施加第一电压到铁电电容器，以及从疲劳测试偏置电​​路向铁电电容器施加第二电压的第二测试。

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