First and second ferroelectric capacitors are selectively connected with a first bit line. Data is read to the first bit line from a first ferroelectric capacitor by applying a first voltage in a coordinate increasing direction of an axis or from the second ferroelectric capacitor by applying a second voltage having a sign opposite to the first voltage in the coordinate increasing direction. Third and fourth ferroelectric capacitors are selectively connected with a second bit line. Data is read to the second bit line from the third ferroelectric capacitor by applying a third voltage having the same sign as the first voltage in the coordinate increasing direction or from the fourth ferroelectric capacitor by applying a fourth voltage having the same sign as the second voltage in the coordinate increasing direction. A sense amplifier amplifies the potential difference between the first and second bit lines.