公开(公告)号：US07161202B2

公开(公告)日：2007-01-09

申请号：US10738999

申请日：2003-12-19

申请人： Katsuhiko Hoya ,  Daisaburo Takashima

发明人： Katsuhiko Hoya ,  Daisaburo Takashima

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/11507 ,  H01L21/76895 ,  H01L27/11502

摘要： First and second ferroelectric capacitors are selectively connected with a first bit line. Data is read to the first bit line from a first ferroelectric capacitor by applying a first voltage in a coordinate increasing direction of an axis or from the second ferroelectric capacitor by applying a second voltage having a sign opposite to the first voltage in the coordinate increasing direction. Third and fourth ferroelectric capacitors are selectively connected with a second bit line. Data is read to the second bit line from the third ferroelectric capacitor by applying a third voltage having the same sign as the first voltage in the coordinate increasing direction or from the fourth ferroelectric capacitor by applying a fourth voltage having the same sign as the second voltage in the coordinate increasing direction. A sense amplifier amplifies the potential difference between the first and second bit lines.

摘要翻译： 第一和第二铁电电容器选择性地与第一位线连接。 通过在坐标增加方向施加具有与第一电压相反的符号的第二电压，通过在轴的坐标增加方向上施加第一电压或从第二铁电电容器向第一位线读取数据到第一位线 。 第三和第四铁电电容器选择性地与第二位线连接。 通过施加具有与第二电压相同的符号的第四电压，通过施加具有与坐标增加方向上的第一电压相同的符号的第三电压或从第四铁电电容器向第二位线读取数据到第二位线 在坐标增加方向。 读出放大器放大第一和第二位线之间的电位差。

公开(公告)号：US06993691B2

公开(公告)日：2006-01-31

申请号：US10120146

申请日：2002-04-11

申请人： Ryu Ogiwara ,  Daisaburo Takashima ,  Yukihito Oowaki ,  Katsuhiko Hoya ,  Takeshi Watanabe

发明人： Ryu Ogiwara ,  Daisaburo Takashima ,  Yukihito Oowaki ,  Katsuhiko Hoya ,  Takeshi Watanabe

IPC分类号： G11C29/00

CPC分类号： G11C8/08 ,  G11C11/22

摘要： Potential of a word line connected to any selected one of memory cells is lowered and potential of word lines connected to non-selected memory cells are raised. The potential of the plate line is raised and lowered. The potential of the bit line is raised and lowered. After this, reading data from the memory cells after potential raising and lowering of the plate line and potential raising and lowering of the bit line have been alternately performed at least one time, thereby to determine attenuation of polarization in the ferroelectric capacitor.

公开(公告)号：US06822891B1

公开(公告)日：2004-11-23

申请号：US10461367

申请日：2003-06-16

申请人： Katsuhiko Hoya ,  Daisaburo Takashima ,  Nobert Rehm

发明人： Katsuhiko Hoya ,  Daisaburo Takashima ,  Nobert Rehm

IPC分类号： G11C700

CPC分类号： G11C11/22

摘要： A ferroelectric memory device includes a memory cell array having memory cells arranged in a matrix form. Each of the memory cells includes a cell transistor and a ferroelectric capacitor. It further includes a first dummy bit line arranged outside a bit line arranged on an end portion of the memory cell array and separated from the bit line arranged on the end portion of the memory cell array with an interval which is the same as a pitch between the bit lines in the memory cell array and having the same width as the bit line, and a first dummy memory cell connected to the first dummy bit line and having the same structure as the memory cell.

摘要翻译： 铁电存储器件包括具有以矩阵形式布置的存储单元的存储单元阵列。 每个存储单元包括单元晶体管和铁电电容器。 其还包括布置在存储单元阵列的端部上的位线之外的第一虚位位线，并且以与间隔相等的间隔与存储单元阵列的端部分布的位线分开， 存储单元阵列中的位线并且具有与位线相同的宽度，以及连接到第一虚拟位线并具有与存储单元相同结构的第一虚拟存储单元。

公开(公告)号：US20080084730A1

公开(公告)日：2008-04-10

申请号：US11902873

申请日：2007-09-26

申请人： Katsuhiko Hoya ,  Daisaburo Takashima

发明人： Katsuhiko Hoya ,  Daisaburo Takashima

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： The memory cell array includes a memory cell, the memory cell including a ferroelectric capacitor and a transistor. The memory cell array includes a word line selecting the memory cell, a plate line applying a drive voltage to the ferroelectric capacitor, and a bit line reading data from the ferroelectric capacitor. A selection transistor selectively connects the memory cell to the bit line. A dummy cell provides a reference potential, the reference potential being referred to for a potential read from the memory cell. A sense amplifier circuit includes a plurality of amplification circuits amplifying the potential difference between a bit-line pair. A decoupling circuit electrically cuts off the bit line between the amplification circuits.

摘要翻译： 存储单元阵列包括存储单元，存储单元包括铁电电容器和晶体管。 存储单元阵列包括选择存储单元的字线，向铁电电容器施加驱动电压的板线和从铁电电容器读取数据的位线。 选择晶体管选择性地将存储单元连接到位线。 虚拟单元提供参考电位，参考电位参考从存储单元读取的电位。 读出放大器电路包括放大位线对之间的电位差的多个放大电路。 去耦电路电切断放大电路之间的位线。

公开(公告)号：US20070058414A1

公开(公告)日：2007-03-15

申请号：US11392614

申请日：2006-03-30

申请人： Katsuhiko Hoya ,  Shinichiro Shiratake ,  Daisaburo Takashima

发明人： Katsuhiko Hoya ,  Shinichiro Shiratake ,  Daisaburo Takashima

IPC分类号： G11C11/22

CPC分类号： G11C11/22 ,  G06F11/1044

摘要： A semiconductor memory device includes a memory cell including a ferroelectric capacitor and a cell transistor and storing binary data at a first potential level and a second potential level which is higher than the first potential level, a bit line which reads the binary data from the memory cell, a correction circuit which corrects an error of the binary data read from the memory cell via the bit line, and a setting circuit which sets to the first potential a potential of the bit line connected to the memory cell from which at least the binary data is read, after the binary data is transferred to the correction circuit. The device further includes a control circuit which controls the potential of the bit line connected to the memory cell from which the binary data is read, in accordance with a result of error correction of the binary data.

摘要翻译： 半导体存储器件包括：存储单元，其包括铁电电容器和单元晶体管，并存储第二电位电平和第二电位高于第一电位电平的二进制数据;从存储器读出二进制数据的位线 单元，校正经由位线从存储单元读取的二进制数据的误差的校正电路，以及设置电路，其将连接到存储单元的位线的电位设置为第一电位，至少二进制 在将二进制数据传送到校正电路之后，读取数据。 该装置还包括控制电路，该控制电路根据二进制数据的纠错结果来控制连接到从其读取二进制数据的存储单元的位线的电位。

公开(公告)号：US06930908B2

公开(公告)日：2005-08-16

申请号：US10721420

申请日：2003-11-26

申请人： Katsuhiko Hoya ,  Daisaburo Takashima

发明人： Katsuhiko Hoya ,  Daisaburo Takashima

IPC分类号： G11C11/22 ,  H01L21/8246 ,  H01L27/105

CPC分类号： G11C11/22

摘要： A semiconductor integrated circuit device includes unit cells, memory cell blocks, bit lines, word lines, block select signal lines, plate lines, and a plate line driver. The unit cell includes a cell transistor and a ferroelectric capacitor connected between a source and a drain of the cell transistor. The memory cell block includes the unit cells connected in series between a first terminal and a second terminal and a block select transistor connected between the second terminal and a third terminal. The bit line connects commonly the third terminals of the blocks. The word line connects commonly gates of cell transistors in the blocks. The block select signal line connects commonly gates of block select transistors in the blocks. The plate line connects commonly the first terminals of the blocks. The plate line driver is connected to the plate lines and applies a potential to the plate lines.

公开(公告)号：US20050047188A1

公开(公告)日：2005-03-03

申请号：US10963589

申请日：2004-10-14

申请人： Katsuhiko Hoya ,  Daisaburo Takashima ,  Nobert Rehm

发明人： Katsuhiko Hoya ,  Daisaburo Takashima ,  Nobert Rehm

IPC分类号： G11C7/00 ,  G11C11/08 ,  G11C11/22

CPC分类号： G11C11/22

摘要： A ferroelectric memory device includes a memory cell array having memory cells arranged in a matrix form. Each of the memory cells includes a cell transistor and a ferroelectric capacitor. It further includes a first dummy bit line arranged outside a bit line arranged on an end portion of the memory cell array and separated from the bit line arranged on the end portion of the memory cell array with an interval which is the same as a pitch between the bit lines in the memory cell array and having the same width as the bit line, and a first dummy memory cell connected to the first dummy bit line and having the same structure as the memory cell.

摘要翻译： 铁电存储器件包括具有以矩阵形式布置的存储单元的存储单元阵列。 每个存储单元包括单元晶体管和铁电电容器。 其还包括布置在存储单元阵列的端部上的位线之外的第一虚位位线，并且以与间隔相等的间隔与存储单元阵列的端部分布的位线分开， 存储单元阵列中的位线并且具有与位线相同的宽度，以及连接到第一虚拟位线并具有与存储单元相同结构的第一虚拟存储单元。

公开(公告)号：US06493251B2

公开(公告)日：2002-12-10

申请号：US09948038

申请日：2001-09-07

申请人： Katsuhiko Hoya ,  Daisaburo Takashima

发明人： Katsuhiko Hoya ,  Daisaburo Takashima

IPC分类号： G11C1122

CPC分类号： G11C11/22

摘要： A series connected unit type ferroelectric memory device is provided, in which a substantially constant read signal margin can be obtained regardless of the position of the selected word line. A memory cell includes a parallel-connected ferroelectric capacitor and cell transistor. Cell blocks each include a plurality of series-connected memory cells arranged between terminals along a pair of bit lines. Some terminals are connected to the bit lines via block selecting transistors. Other terminals are connected to the plate lines. A gate of each cell transistor is connected to a word line. A sense amplifier is connected to the bit lines. When data is read, an offset voltage applying circuit compensates for the imbalance in read signal margin caused by the difference in position of the word line by applying to the bit line an offset voltage which differs depending on the position of the selected word line.

摘要翻译： 提供了一种串联连接单元型铁电存储器件，其中可以获得基本上恒定的读取信号余量，而不管所选字线的位置如何。 存储单元包括并联连接的铁电电容器和单元晶体管。 单元块各自包括沿着一对位线布置在端子之间的多个串联存储单元。 一些端子通过块选择晶体管连接到位线。 其他端子连接到板线。 每个单元晶体管的栅极连接到字线。 读出放大器连接到位线。 当读取数据时，偏移电压施加电路通过向位线施加由所选字线的位置而不同的偏移电压来补偿由字线的位置差引起的读信号余量的不平衡。

公开(公告)号：US07872899B2

公开(公告)日：2011-01-18

申请号：US11902873

申请日：2007-09-26

申请人： Katsuhiko Hoya ,  Daisaburo Takashima

发明人： Katsuhiko Hoya ,  Daisaburo Takashima

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： The memory cell array includes a memory cell, the memory cell including a ferroelectric capacitor and a transistor. The memory cell array includes a word line selecting the memory cell, a plate line applying a drive voltage to the ferroelectric capacitor, and a bit line reading data from the ferroelectric capacitor. A selection transistor selectively connects the memory cell to the bit line. A dummy cell provides a reference potential, the reference potential being referred to for a potential read from the memory cell. A sense amplifier circuit includes a plurality of amplification circuits amplifying the potential difference between a bit-line pair. A decoupling circuit electrically cuts off the bit line between the amplification circuits.

摘要翻译： 存储单元阵列包括存储单元，存储单元包括铁电电容器和晶体管。 存储单元阵列包括选择存储单元的字线，向铁电电容器施加驱动电压的板线和从铁电电容器读取数据的位线。 选择晶体管选择性地将存储单元连接到位线。 虚拟单元提供参考电位，参考电位参考从存储单元读取的电位。 读出放大器电路包括放大位线对之间的电位差的多个放大电路。 去耦电路电切断放大电路之间的位线。

公开(公告)号：US20050013156A1

公开(公告)日：2005-01-20

申请号：US10721420

申请日：2003-11-26

申请人： Katsuhiko Hoya ,  Daisaburo Takashima

发明人： Katsuhiko Hoya ,  Daisaburo Takashima

IPC分类号： G11C11/22 ,  H01L21/8246 ,  H01L27/105

CPC分类号： G11C11/22

摘要： A semiconductor integrated circuit device includes unit cells, memory cell blocks, bit lines, word lines, block select signal lines, plate lines, and a plate line driver. The unit cell includes a cell transistor and a ferroelectric capacitor connected between a source and a drain of the cell transistor. The memory cell block includes the unit cells connected in series between a first terminal and a second terminal and a block select transistor connected between the second terminal and a third terminal. The bit line connects commonly the third terminals of the blocks. The word line connects commonly gates of cell transistors in the blocks. The block select signal line connects commonly gates of block select transistors in the blocks. The plate line connects commonly the first terminals of the blocks. The plate line driver is connected to the plate lines and applies a potential to the plate lines.

摘要翻译： 半导体集成电路装置包括单位单元，存储单元块，位线，字线，块选择信号线，板线和板线驱动器。 单元电池包括连接在单元晶体管的源极和漏极之间的单元晶体管和铁电电容器。 存储单元块包括串联连接在第一端子和第二端子之间的单元电池以及连接在第二端子和第三端子之间的块选择晶体管。 位线通常连接块的第三个端子。 字线连接块中的单元晶体管的通用栅极。 块选择信号线连接块中的块选择晶体管的共同门。 板线通常连接块的第一个端子。 板线驱动器连接到板条线并向板线施加电位。