公开(公告)号：US20080079107A1

公开(公告)日：2008-04-03

申请号：US11983859

申请日：2007-11-12

申请人： John Snyder ,  John Larson

发明人： John Snyder ,  John Larson

IPC分类号： H01L31/107

CPC分类号： H01L29/0847 ,  H01L21/28194 ,  H01L21/823412 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/47 ,  H01L29/51 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66643 ,  H01L29/7839

摘要： The present invention is a field effect transistor having a strained semiconductor substrate and Schottky-barrier source and drain electrodes, and a method for making the transistor. The bulk charge carrier transport characteristic of the Schottky barrier field effect transistor minimizes carrier surface scattering, which enables the strained substrate to provide improved power and speed performance characteristics in this device, as compared to conventional devices.

摘要翻译： 本发明是具有应变半导体衬底和肖特基势垒源极和漏极的场效应晶体管及其制造方法。 与传统器件相比，肖特基势垒场效应晶体管的体电荷载流子传输特性使载流子表面散射最小化，这使得应变衬底能够在该器件中提供改进的功率和速度性能特性。

公开(公告)号：US20070007605A1

公开(公告)日：2007-01-11

申请号：US11455905

申请日：2006-06-19

申请人： John Snyder ,  John Larson

发明人： John Snyder ,  John Larson

IPC分类号： H01L29/94

CPC分类号： H01L21/28194 ,  H01L21/26513 ,  H01L21/28167 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/823412 ,  H01L27/095 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/47 ,  H01L29/51 ,  H01L29/511 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66643 ,  H01L29/7839

摘要： The invention is directed to a device for regulating the flow of electric current with high dielectric constant gate insulating layer and a source and/or drain forming a Schottky contact or Schottky-like region with a substrate and its fabrication method. In one aspect, the gate insulating layer has a dielectric constant greater than the dielectric constant of silicon. In another aspect, the current regulating device may be a MOSFET device, optionally a planar P-type or N-type MOSFET, having any orientation. In another aspect, the source and/or drain may consist partially or fully of a silicide.

摘要翻译： 本发明涉及一种用于通过高介电常数栅极绝缘层和形成具有衬底的肖特基接触或肖特基状区域的源极和/或漏极来调节电流的装置及其制造方法。 在一个方面，栅极绝缘层的介电常数大于硅的介电常数。 在另一方面，电流调节装置可以是具有任何取向的MOSFET器件，可选地是平面P型或N型MOSFET。 在另一方面，源极和/或漏极可部分或全部由硅化物组成。

公开(公告)号：US20060237752A1

公开(公告)日：2006-10-26

申请号：US11388781

申请日：2006-03-24

申请人： John Larson ,  John Snyder

发明人： John Larson ,  John Snyder

IPC分类号： H01L29/80

CPC分类号： H01L21/823814 ,  H01L27/095 ,  H01L29/66643 ,  H01L29/7839

摘要： A Schottky barrier integrated circuit is disclosed, the circuit having at least one PMOS device or at least one NMOS device, at least one of the PMOS device or NMOS device having metal source-drain contacts forming Schottky barrier or Schottky-like contacts to the semiconductor substrate. The device provides a lower capacitance between source and gate, which improves device and circuit power and speed performance.

摘要翻译： 公开了一种肖特基势垒集成电路，该电路具有至少一个PMOS器件或至少一个NMOS器件，PMOS器件或NMOS器件中的至少一个具有金属源极 - 漏极接触，形成肖特基势垒或肖特基接触到半导体 基质。 该器件在源极和栅极之间提供较低的电容，从而提高器件和电路的功率和速度性能。

公开(公告)号：US20050106821A1

公开(公告)日：2005-05-19

申请号：US10958627

申请日：2004-10-05

申请人： John Snyder ,  John Larson

发明人： John Snyder ,  John Larson

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/095 ,  H01L29/10 ,  H01L29/417 ,  H01L29/47 ,  H01L29/51 ,  H01L29/78 ,  H01L31/0328

CPC分类号： H01L21/28194 ,  H01L21/26513 ,  H01L21/28167 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/823412 ,  H01L27/095 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/47 ,  H01L29/51 ,  H01L29/511 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66643 ,  H01L29/7839

摘要： The invention is directed to a device for regulating the flow of electric current with high dielectric constant gate insulating layer and a source and/or drain forming a Schottky contact or Schottky-like region with a substrate and its fabrication method. In one aspect, the gate insulating layer has a dielectric constant greater than the dielectric constant of silicon. In another aspect, the current regulating device may be a MOSFET device, optionally a planar P-type or N-type MOSFET, having any orientation. In another aspect, the source and/or drain may consist partially or fully of a silicide.

公开(公告)号：US20050003595A1

公开(公告)日：2005-01-06

申请号：US10893190

申请日：2004-07-16

申请人： John Snyder ,  John Larson

发明人： John Snyder ,  John Larson

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/417 ,  H01L29/47 ,  H01L29/51 ,  H01L29/78 ,  H01L29/786 ,  H01L29/872 ,  H01L21/338 ,  H01L29/76

CPC分类号： H01L29/0847 ,  H01L21/28194 ,  H01L21/823412 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/47 ,  H01L29/51 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66643 ,  H01L29/7839

摘要： The present invention is a field effect transistor having a strained semiconductor substrate and Schottky-barrier source and drain electrodes, and a method for making the transistor. The bulk charge carrier transport characteristic of the Schottky barrier field effect transistor minimizes carrier surface scattering, which enables the strained substrate to provide improved power and speed performance characteristics in this device, as compared to conventional devices.

摘要翻译： 本发明是具有应变半导体衬底和肖特基势垒源极和漏极的场效应晶体管及其制造方法。 与传统器件相比，肖特基势垒场效应晶体管的体电荷载流子传输特性使载流子表面散射最小化，这使得应变衬底能够在该器件中提供改进的功率和速度性能特性。

公开(公告)号：US20070080406A1

公开(公告)日：2007-04-12

申请号：US11546829

申请日：2006-10-12

申请人： John Snyder ,  John Larson

发明人： John Snyder ,  John Larson

IPC分类号： H01L29/94

CPC分类号： H01L21/823892 ,  H01L21/823814 ,  H01L27/0921 ,  H01L29/66636 ,  H01L29/66643 ,  H01L29/7839

摘要： A CMOS device and method of manufacture is provided for producing an integrated circuit that is not susceptible to various soft errors such as single-event upsets, multi-bit upsets or single-event latchup. The CMOS device and method utilizes a new and novel well architecture in conjunction with metal source/drain electrodes to eliminate soft errors. In one embodiment, the CMOS device uses a first metal source/drain material for the NMOS device and a second metal source/drain material for the PMOS device. The CMOS device further uses a multi-layered well-structure with a shallow N-well and a buried P-well for the PMOS device and a shallow P-well and a buried N-well for the NMOS device.

摘要翻译： 提供了一种CMOS器件和制造方法，用于产生不易受各种软错误（例如单事件颠簸，多位异常或单事件闭锁）的集成电路的影响。 CMOS器件和方法利用新的和新颖的结构与金属源极/漏电极的结构，以消除软错误。 在一个实施例中，CMOS器件使用用于NMOS器件的第一金属源/漏极材料和用于PMOS器件的第二金属源极/漏极材料。 CMOS器件还使用具有用于PMOS器件的浅N阱和掩埋P阱的多层阱结构以及用于NMOS器件的浅P阱和掩埋N阱。

公开(公告)号：US20060079059A1

公开(公告)日：2006-04-13

申请号：US11235682

申请日：2005-09-26

申请人： John Snyder ,  John Larson

发明人： John Snyder ,  John Larson

IPC分类号： H01L21/336

CPC分类号： H01L21/28167 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823412 ,  H01L27/095 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/47 ,  H01L29/51 ,  H01L29/511 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66643 ,  H01L29/7839

摘要： The invention is directed to a device for regulating the flow of electric current with high dielectric constant gate insulating layer and a source and/or drain forming a Schottky contact or Schottky-like region with a substrate and its fabrication method. In one aspect, the gate insulating layer has a dielectric constant greater than the dielectric constant of silicon. In another aspect, the current regulating device may be a MOSFET device, optionally a planar P-type or N-type MOSFET, having any orientation. In another aspect, the source and/or drain may consist partially or fully of a silicide.

公开(公告)号：US20050139860A1

公开(公告)日：2005-06-30

申请号：US10970688

申请日：2004-10-21

申请人： John Snyder ,  John Larson

发明人： John Snyder ,  John Larson

IPC分类号： H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/74 ,  H01L21/425

CPC分类号： H01L29/66643 ,  H01L29/0653 ,  H01L29/0895 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7839

摘要： A device for regulating a flow of electric current and its manufacturing method are provided. The device includes metal-insulator-semiconductor source-drain contacts forming Schottky barrier or Schottky-like junctions to the semiconductor substrate. The device includes an interfacial layer between the semiconductor substrate and a metal source and/or drain electrode, thereby dynamically adjusting a Schottky barrier height by applying different bias conditions. The dynamic Schottky barrier modulation provides increased electric current for low drain bias conditions, reducing the sub-linear turn-on characteristic of Schottky barrier MOSFET devices and improving device performance.

摘要翻译： 提供一种用于调节电流流动的装置及其制造方法。 该器件包括形成肖特基势垒或肖特基状结到半导体衬底的金属 - 绝缘体 - 半导体源极 - 漏极接触。 该器件包括在半导体衬底和金属源极和/或漏极之间的界面层，从而通过施加不同的偏置条件来动态地调节肖特基势垒高度。 动态肖特基势垒调制为低漏极偏置条件提供了增加的电流，降低了肖特基势垒MOSFET器件的亚线性导通特性并提高器件性能。

公开(公告)号：US20070026590A1

公开(公告)日：2007-02-01

申请号：US11543631

申请日：2006-10-05

申请人： John Snyder ,  John Larson

发明人： John Snyder ,  John Larson

IPC分类号： H01L31/07 ,  H01L27/095 ,  H01L31/108 ,  H01L29/47 ,  H01L29/812 ,  H01L21/338

CPC分类号： H01L29/66643 ,  H01L29/0653 ,  H01L29/0895 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7839

摘要： A device for regulating a flow of electric current and its manufacturing method are provided. The device includes metal-insulator-semiconductor source-drain contacts forming Schottky barrier or Schottky-like junctions to the semiconductor substrate. The device includes an interfacial layer between the semiconductor substrate and a metal source and/or drain electrode, thereby dynamically adjusting a Schottky barrier height by applying different bias conditions. The dynamic Schottky barrier modulation provides increased electric current for low drain bias conditions, reducing the sub-linear turn-on characteristic of Schottky barrier MOSFET devices and improving device performance.

摘要翻译： 提供一种用于调节电流流动的装置及其制造方法。 该器件包括形成肖特基势垒或肖特基状结到半导体衬底的金属 - 绝缘体 - 半导体源极 - 漏极接触。 该器件包括在半导体衬底和金属源极和/或漏极之间的界面层，从而通过施加不同的偏置条件来动态地调节肖特基势垒高度。 动态肖特基势垒调制为低漏极偏置条件提供了增加的电流，降低了肖特基势垒MOSFET器件的亚线性导通特性并提高器件性能。

公开(公告)号：US20060244052A1

公开(公告)日：2006-11-02

申请号：US11478478

申请日：2006-06-28

申请人： John Snyder ,  John Larson

发明人： John Snyder ,  John Larson

IPC分类号： H01L29/78

CPC分类号： H01L27/095 ,  H01L21/2652 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/105 ,  H01L29/47 ,  H01L29/665 ,  H01L29/66643 ,  H01L29/7839

摘要： A MOSFET device and method of fabricating is provided. The MOSFET device and method of fabricating utilizes Schottky barrier contacts for source and/or drain contact fabrication within the context of a MOSFET device structure to eliminate the requirement for halo/pocket implants and shallow source/drain extensions to control short channel effects. Additionally, the MOSFET device and method unconditionally eliminates the parasitic bipolar gain associated with MOSFET fabrication, reduces manufacturing costs, tightens control of device performance parameters, and provides for superior device characteristics.

摘要翻译： 提供了一种MOSFET器件及其制造方法。 MOSFET器件和制造方法在MOSFET器件结构的上下文中利用用于源极和/或漏极接触制造的肖特基势垒接触，以消除对光晕/凹穴注入的需要和浅的源/漏扩展以控制短沟道效应。 此外，MOSFET器件和方法无条件地消除了与MOSFET制造相关的寄生双极增益，降低了制造成本，加强了器件性能参数的控制，并提供了卓越的器件特性。