公开(公告)号：US20090149016A1

公开(公告)日：2009-06-11

申请号：US12330416

申请日：2008-12-08

Applicant: Jin-Woo PARK ,  Tae-Joo HWANG ,  Nam-Seog KIM

Inventor： Jin-Woo PARK ,  Tae-Joo HWANG ,  Nam-Seog KIM

IPC: H01L21/768

CPC classification number: H01L24/11 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/10126 ,  H01L2224/1308 ,  H01L2224/13099 ,  H01L2224/13565 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Provided is a semiconductor device and a method of fabricating the same. The method of fabricating the semiconductor device includes forming a mask pattern having an opening corresponding to an electrode pad formed on a semiconductor substrate; forming a bump by filling the opening with a conductive first material; forming a sidewall film on sidewalls of the bump using a second material; forming a connection member between an upper surface of the bump and a wire substrate using a conductive third material in order to electrically connect the bump and the wire substrate; and forming an underfill resin between the wire substrate and the semiconductor substrate, wherein a wetting angle between the second material and the third material is greater than that between the first material and the third material.

Abstract translation: 提供一种半导体器件及其制造方法。 制造半导体器件的方法包括形成具有对应于形成在半导体衬底上的电极焊盘的开口的掩模图案; 通过用导电的第一材料填充开口形成凸起; 使用第二材料在所述凸块的侧壁上形成侧壁膜; 在所述突起的上表面和使用导电的第三材料的金属基底之间形成连接构件，以便电连接所述凸块和所述金属丝基底; 以及在所述金属丝衬底和所述半导体衬底之间形成底部填充树脂，其中所述第二材料和所述第三材料之间的润湿角度大于所述第一材料和所述第三材料之间的润湿角度。

公开(公告)号：US20160148913A1

公开(公告)日：2016-05-26

申请号：US15010826

申请日：2016-01-29

Applicant: Tae-Joo HWANG ,  Tae-Gyeong CHUNG ,  Eun-Chul AHN

Inventor： Tae-Joo HWANG ,  Tae-Gyeong CHUNG ,  Eun-Chul AHN

IPC: H01L25/10

CPC classification number: H01L23/49811 ,  H01L23/481 ,  H01L24/06 ,  H01L24/16 ,  H01L24/29 ,  H01L24/31 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/078 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including first through hole vias, and a chip package disposed on the first semiconductor chip, the chip package including a second package substrate and a second semiconductor chip disposed on the second package substrate, wherein a first conductive terminal is disposed on a first surface of the semiconductor chip and a second conductive terminal is disposed on a first surface of the second package substrate, the first conductive terminal disposed on the second conductive terminal.

公开(公告)号：US20160064357A1

公开(公告)日：2016-03-03

申请号：US14825403

申请日：2015-08-13

Applicant: Yeong-Hwan CHOE ,  Tae-Joo HWANG ,  Tae-Hong MIN ,  Young-Kun JEE ,  Sang-Uk HAN

Inventor： Yeong-Hwan CHOE ,  Tae-Joo HWANG ,  Tae-Hong MIN ,  Young-Kun JEE ,  Sang-Uk HAN

IPC: H01L25/065 ,  H01L23/48 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/10 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/71 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/06156 ,  H01L2224/10125 ,  H01L2224/131 ,  H01L2224/14156 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75305 ,  H01L2224/81007 ,  H01L2224/81191 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/014

Abstract: A semiconductor device includes at least first and second semiconductor chips stacked on each other along a first direction, at least one silicon-through-via (TSV) through at least the first semiconductor chip of the first and second semiconductor chips, a contact pad on the at least one TSV of the first semiconductor chip, the contact pad electrically connecting the TSV of the first semiconductor chip to the second semiconductor chip, and a plurality of dummy pads on the first semiconductor chip, the plurality of dummy pads being spaced apart from each other and from the contact pad along a second direction, and the dummy pads having same heights as the contact pads as measured between respective top and bottom surfaces along the first direction.

Abstract translation: 半导体器件至少包括沿着第一方向彼此堆叠的第一和第二半导体芯片，至少一个硅通孔（TSV），至少通过第一和第二半导体芯片的第一半导体芯片，接触焊盘 所述第一半导体芯片的所述至少一个TSV，所述接触焊盘将所述第一半导体芯片的TSV电连接到所述第二半导体芯片，以及所述第一半导体芯片上的多个虚拟焊盘，所述多个虚拟焊盘与所述第一半导体芯片间隔开 彼此并且沿着第二方向从接触焊盘接合，并且虚拟焊盘具有与沿着第一方向在相应的顶部和底部表面之间测量的接触焊盘相同的高度。

公开(公告)号：US20140235017A1

公开(公告)日：2014-08-21

申请号：US14263385

申请日：2014-04-28

Applicant: Tae-Joo HWANG ,  Tae-Gyeong CHUNG ,  Eun-Chul AHN

Inventor： Tae-Joo HWANG ,  Tae-Gyeong CHUNG ,  Eun-Chul AHN

IPC: H01L23/00

CPC classification number: H01L23/49811 ,  H01L23/481 ,  H01L24/06 ,  H01L24/16 ,  H01L24/29 ,  H01L24/31 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/078 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including first through hole vias, and a chip package disposed on the first semiconductor chip, the chip package including a second package substrate and a second semiconductor chip disposed on the second package substrate, wherein a first conductive terminal is disposed on a first surface of the semiconductor chip and a second conductive terminal is disposed on a first surface of the second package substrate, the first conductive terminal disposed on the second conductive terminal.

Abstract translation: 半导体封装包括第一封装衬底，设置在第一封装衬底上的第一半导体芯片，包括第一通孔通孔的半导体芯片和设置在第一半导体芯片上的芯片封装，芯片封装包括第二封装衬底和 设置在所述第二封装基板上的第二半导体芯片，其中，第一导电端子设置在所述半导体芯片的第一表面上，并且第二导电端子设置在所述第二封装基板的第一表面上，所述第一导电端子设置在所述第二封装基板的第二表面上 导电端子。

公开(公告)号：US20120223427A1

公开(公告)日：2012-09-06

申请号：US13470572

申请日：2012-05-14

Applicant: Jong-Joo LEE ,  Tae-Joo HWANG ,  Cha-Jea JO

Inventor： Jong-Joo LEE ,  Tae-Joo HWANG ,  Cha-Jea JO

IPC: H01L23/485

CPC classification number: H01L23/49816 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05018 ,  H01L2224/05085 ,  H01L2224/05558 ,  H01L2224/0603 ,  H01L2224/06136 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00012

Abstract: A flip chip package may include a substrate, a semiconductor chip, main bump structures and auxiliary bump structures. The substrate has a circuit pattern. The semiconductor chip is arranged over the substrate. The semiconductor chip includes a body having semiconductor structures, main pads electrically connected to the semiconductor structures to mainly control the semiconductor structures, and auxiliary pads electrically connected to the semiconductor structures to provide auxiliary control of the semiconductor structures. The main bump structures are interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the main pads. The auxiliary bump structures can be interposed between the semiconductor chip and the substrate to electrically connect the circuit pattern with the auxiliary pads.

Abstract translation: 倒装芯片封装可以包括衬底，半导体芯片，主凸块结构和辅助凸块结构。 基板具有电路图案。 半导体芯片布置在衬底上。 半导体芯片包括具有半导体结构的主体，电连接到半导体结构以主要控制半导体结构的主焊盘以及与半导体结构电连接以提供半导体结构的辅助控制的辅助焊盘。 主凸块结构插入在半导体芯片和基板之间以将电路图案与主焊盘电连接。 辅助凸块结构可以插入在半导体芯片和衬底之间以将电路图案与辅助焊盘电连接。

公开(公告)号：US20080122084A1

公开(公告)日：2008-05-29

申请号：US11946750

申请日：2007-11-28

Applicant: Tae-Joo HWANG ,  Eun-Chul AHN ,  Tae-Gyeong CHUNG

Inventor： Tae-Joo HWANG ,  Eun-Chul AHN ,  Tae-Gyeong CHUNG

IPC: H01L23/48 ,  H01L21/58

CPC classification number: H01L24/90 ,  H01L23/3171 ,  H01L24/83 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/274 ,  H01L2224/32225 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A flip-chip assembly comprises a semiconductor chip, a substrate, a first buffer layer, a second buffer layer and a conductive bump. The semiconductor chip includes a first region and a second region adjacent to the first region. The substrate is disposed under the semiconductor chip. The first buffer layer is disposed between the first region of the semiconductor chip and the substrate. The second buffer layer is disposed between the second region of the semiconductor chip and the substrate. The conductive bump is formed through the second buffer layer and electrically connects the semiconductor chip to the substrate.

Abstract translation: 倒装芯片组件包括半导体芯片，衬底，第一缓冲层，第二缓冲层和导电凸块。 半导体芯片包括与第一区域相邻的第一区域和第二区域。 衬底设置在半导体芯片下方。 第一缓冲层设置在半导体芯片的第一区域和基板之间。 第二缓冲层设置在半导体芯片的第二区域和基板之间。 导电凸块通过第二缓冲层形成并将半导体芯片电连接到基板。

公开(公告)号：US20170330862A1

公开(公告)日：2017-11-16

申请号：US15662764

申请日：2017-07-28

Applicant: Yeong-Hwan CHOE ,  Tae-Joo HWANG ,  Tae-Hong MIN ,  Young-Kun JEE ,  Sang-Uk HAN

Inventor： Yeong-Hwan CHOE ,  Tae-Joo HWANG ,  Tae-Hong MIN ,  Young-Kun JEE ,  Sang-Uk HAN

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/10 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/71 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/06156 ,  H01L2224/10125 ,  H01L2224/131 ,  H01L2224/14156 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75305 ,  H01L2224/81007 ,  H01L2224/81191 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/014

Abstract: A semiconductor device includes at least first and second semiconductor chips stacked on each other along a first direction, at least one through-silicon-via (TSV) through at least the first semiconductor chip of the first and second semiconductor chips, a contact pad on the at least one TSV of the first semiconductor chip, the contact pad electrically connecting the TSV of the first semiconductor chip to the second semiconductor chip, and a plurality of dummy pads on the first semiconductor chip, the plurality of dummy pads being spaced apart from each other and from the contact pad along a second direction, and the dummy pads having same heights as the contact pads as measured between respective top and bottom surfaces along the first direction.

公开(公告)号：US20130200515A1

公开(公告)日：2013-08-08

申请号：US13785811

申请日：2013-03-05

Applicant: Tae-Joo HWANG ,  Tae-gyeong Chung ,  Eun-chul Ahn

Inventor： Tae-Joo HWANG ,  Tae-gyeong Chung ,  Eun-chul Ahn

IPC: H01L23/498

CPC classification number: H01L23/49811 ,  H01L23/481 ,  H01L24/06 ,  H01L24/16 ,  H01L24/29 ,  H01L24/31 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/078 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including first through hole vias, and a chip package disposed on the first semiconductor chip, the chip package including a second package substrate and a second semiconductor chip disposed on the second package substrate, wherein a first conductive terminal is disposed on a first surface of the semiconductor chip and a second conductive terminal is disposed on a first surface of the second package substrate, the first conductive terminal disposed on the second conductive terminal.

Abstract translation: 半导体封装包括第一封装衬底，设置在第一封装衬底上的第一半导体芯片，包括第一通孔通孔的半导体芯片和设置在第一半导体芯片上的芯片封装，芯片封装包括第二封装衬底和 设置在所述第二封装基板上的第二半导体芯片，其中，第一导电端子设置在所述半导体芯片的第一表面上，并且第二导电端子设置在所述第二封装基板的第一表面上，所述第一导电端子设置在所述第二封装基板的第二表面上 导电端子。

公开(公告)号：US20080268579A1

公开(公告)日：2008-10-30

申请号：US12110215

申请日：2008-04-25

Applicant: Hae-Jung YU ,  Mu-Seob SHIN ,  Tae-Joo HWANG ,  Tae-Gyeong CHUNG ,  Eun-Chul AHN

Inventor： Hae-Jung YU ,  Mu-Seob SHIN ,  Tae-Joo HWANG ,  Tae-Gyeong CHUNG ,  Eun-Chul AHN

IPC: H01L21/56

CPC classification number: H01L23/3128 ,  H01L21/563 ,  H01L24/16 ,  H01L2224/13099 ,  H01L2224/73203 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A semiconductor chip package capable of improving reliability at a chip interconnection portion and improving reliability in a solder joint by reducing thermal and mechanical stresses at an external portion of the package including a solder ball land, and a method of fabricating the package are provided. The method of fabricating a semiconductor chip package includes providing a substrate; forming a first underfill on a first portion of the substrate; forming a second underfill at a chip interconnection portion of the substrate; and mounting a semiconductor chip on the chip interconnection portion using conductive bumps. In the method, the second underfill is formed of a material having a modulus higher than the first underfill.

Abstract translation: 提供一种半导体芯片封装，其能够通过降低包括焊球面的封装的外部部分处的热和机械应力来提高芯片互连部分的可靠性并提高焊接点的可靠性，并提供制造封装的方法。 制造半导体芯片封装的方法包括提供衬底; 在所述基板的第一部分上形成第一底部填充物; 在所述基板的芯片互连部分处形成第二底部填充物; 以及使用导电凸块将半导体芯片安装在芯片互连部分上。 在该方法中，第二底部填充物由具有高于第一底部填充物的模量的材料形成。

公开(公告)号：US20080006949A1

公开(公告)日：2008-01-10

申请号：US11765367

申请日：2007-06-19

Applicant: Jong-Gi LEE ,  Tae-Joo HWANG

Inventor： Jong-Gi LEE ,  Tae-Joo HWANG

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/16 ,  H01L21/563 ,  H01L23/3114 ,  H01L24/29 ,  H01L2224/16225 ,  H01L2224/73203 ,  H01L2224/83191 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/3512 ,  H01L2924/00

Abstract: Provided are a semiconductor package and a method of fabricating the same. The semiconductor package includes a semiconductor chip, and a plurality of conductive balls, e.g., solder balls formed on a joint surface of the semiconductor chip. A dummy board includes openings aligned with the solder balls and is bonded to the joint surface of the semiconductor chip. An adhesive material is interposed between the semiconductor chip and the dummy board to adhere the dummy board to the semiconductor chip. The adhesive material is applied on an adhesion surface of the dummy board adhered to a joint surface of the semiconductor chip. The dummy board is adhered to the joint surface of the semiconductor chip such that the solder balls are aligned with the openings. Cheap underfill materials can be selectively used, and a process time for reflow and curing of the adhesive material can be greatly reduced.

Abstract translation: 提供半导体封装及其制造方法。 半导体封装包括半导体芯片和多个导电球，例如形成在半导体芯片的接合表面上的焊球。 虚拟板包括与焊球对准的开口并且结合到半导体芯片的接合表面。 在半导体芯片和虚拟基板之间插入粘合材料，以将该虚拟板粘接到半导体芯片。 将粘合材料施加在粘附到半导体芯片的接合表面的伪板的粘合表面上。 将该虚拟板粘接到半导体芯片的接合面，使得焊球与开口对准。 可以选择性地使用廉价的底部填充材料，并且可以大大降低粘合剂材料的回流和固化的处理时间。