公开(公告)号：US10943863B2

公开(公告)日：2021-03-09

申请号：US16570037

申请日：2019-09-13

申请人： International Business Machines Corporation

发明人： Chao-Kun Hu ,  Christian Lavoie ,  Stephen M. Rossnagel ,  Thomas M. Shaw

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L21/4763 ,  H01L21/44 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

摘要： Techniques for improving reliability in Cu interconnects using Cu intermetallics are provided. In one aspect, a method of forming a Cu interconnect in a dielectric over a Cu line includes the steps of: forming at least one via in the dielectric over the Cu line; depositing a metal layer onto the dielectric and lining the via such that the metal layer is in contact with the Cu line at the bottom of the via, wherein the metal layer comprises at least one metal that can react with Cu to form a Cu intermetallic; annealing the metal layer and the Cu line under conditions sufficient to form a Cu intermetallic barrier at the bottom of the via; and plating Cu into the via to form the Cu interconnect, wherein the Cu interconnect is separated from the Cu line by the Cu intermetallic barrier. A device structure is also provided.

公开(公告)号：US20170010322A1

公开(公告)日：2017-01-12

申请号：US15258535

申请日：2016-09-07

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Jifeng Chen ,  Dirk Pfeiffer ,  Thomas M. Shaw ,  Peilin Song ,  Franco Stellari

IPC分类号： G01R31/28 ,  G01R31/311

CPC分类号： G01R31/2855 ,  G01R31/281 ,  G01R31/2817 ,  G01R31/2858 ,  G01R31/2879 ,  G01R31/311

摘要： Systems for reliability testing include a picometer configured to measure a leakage current across a device under test (DUT); a camera configured to measure optical emissions from the DUT based on a timing of the measurement of the leakage current; and a test system configured to apply a stress voltage to the DUT and to correlate the leakage current with the optical emissions using a processor to determine a time and location of a defect occurrence within the DUT by locating instances of increased noise in the leakage current that correspond in time with instances of increased optical emissions.

摘要翻译： 用于可靠性测试的系统包括配置成测量被测器件（DUT）上的漏电流的波长计; 配置为基于所述泄漏电流的测量的定时来测量来自所述DUT的光发射的照相机; 以及被配置为向DUT施加应力电压并且使用处理器将泄漏电流与光发射相关联的测试系统，以通过定位泄漏电流中增加的噪声的实例来确定DUT内的缺陷发生的时间和位置， 在时间上对应于增加的光发射的情况。

公开(公告)号：US20200006226A1

公开(公告)日：2020-01-02

申请号：US16569997

申请日：2019-09-13

申请人： International Business Machines Corporation

发明人： Chao-Kun Hu ,  Christian Lavoie ,  Stephen M. Rossnagel ,  Thomas M. Shaw

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/532

摘要： Techniques for improving reliability in Cu interconnects using Cu intermetallics are provided. In one aspect, a method of forming a Cu interconnect in a dielectric over a Cu line includes the steps of: forming at least one via in the dielectric over the Cu line; depositing a metal layer onto the dielectric and lining the via such that the metal layer is in contact with the Cu line at the bottom of the via, wherein the metal layer comprises at least one metal that can react with Cu to form a Cu intermetallic; annealing the metal layer and the Cu line under conditions sufficient to form a Cu intermetallic barrier at the bottom of the via; and plating Cu into the via to form the Cu interconnect, wherein the Cu interconnect is separated from the Cu line by the Cu intermetallic barrier. A device structure is also provided.

公开(公告)号：US10168143B2

公开(公告)日：2019-01-01

申请号：US15453431

申请日：2017-03-08

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Anthony J. Annunziata ,  Chandrasekharan Kothandaraman ,  Thomas M. Shaw

IPC分类号： G01B9/02 ,  G01B11/16 ,  H01L27/22 ,  H01L43/08 ,  H01L23/528 ,  G11C29/00 ,  G11C11/16

摘要： A method is presented for determining strain in a magnetoresistive random access memory (MRAM) structure. The method includes exposing long lines of the MRAM structure to monochromatic light to produce a diffraction pattern, measuring changes in interference fringe spacing in the diffraction pattern, determining the changes in the local strain in the MRAM structure from the measured changes in the interference fringe spacing, and assessing a performance of the MRAM structure from values of the changes in the local strain.

公开(公告)号：US20170084413A1

公开(公告)日：2017-03-23

申请号：US14745521

申请日：2015-06-22

申请人： International Business Machines Corporation

发明人： Matthew W. Copel ,  Bruce G. Elmegreen ,  Glenn J. Martyna ,  Dennis M. Newns ,  Thomas M. Shaw ,  Paul M. Solomon

IPC分类号： H01H57/00 ,  H01H49/00

CPC分类号： H01H57/00 ,  H01H49/00 ,  H01H2057/006

摘要： A piezoelectronic switch device for radio frequency (RF) applications includes a piezoelectric (PE) material layer and a piezoresistive (PR) material layer separated from one another by at least one electrode, wherein an electrical resistance of the PR material layer is dependent upon an applied voltage across the PE material layer by way of an applied pressure to the PR material layer by the PE material layer; and a conductive, high yield material (C-HYM) comprising a housing that surrounds the PE material layer, the PR material layer and the at least one electrode, the C-HYM configured to mechanically transmit a displacement of the PE material layer to the PR material layer such that applied voltage across the PE material layer causes an expansion thereof and an increase the applied pressure to the PR material layer, thereby causing a decrease in the electrical resistance of the PR material layer.

公开(公告)号：US09583410B2

公开(公告)日：2017-02-28

申请号：US14221477

申请日：2014-03-21

申请人： International Business Machines Corporation

发明人： Daniel C. Edelstein ,  Michael A. Gaynes ,  Thomas M. Shaw ,  Bucknell C. Webb ,  Roy R. Yu

IPC分类号： H01L23/29 ,  H01L23/31

CPC分类号： H01L23/293 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/3192 ,  H01L2224/11

摘要： A volumetric integrated circuit manufacturing method is provided. The method includes assembling a slab element of elongate chips, exposing a wiring layer between adjacent elongate chips of the slab element, metallizing a surface of the slab element at and around the exposed wiring layer to form a metallized surface electrically coupled to the wiring layer and passivating the metallized surface to hermetically seal the metallized surface.

摘要翻译： 提供了体积集成电路制造方法。 该方法包括组装细长芯片的平板元件，暴露板坯元件的相邻细长芯片之间的布线层，将暴露的布线层周围和周围的平板元件的表面金属化以形成电耦合到布线层的金属化表面，以及 钝化金属化表面以气密地密封金属化表面。

公开(公告)号：US09087805B2

公开(公告)日：2015-07-21

申请号：US14524637

申请日：2014-10-27

申请人： International Business Machines Corporation

发明人： James V. Crain, Jr. ,  Mark C. H. Lamorey ,  Christopher D. Muzzy ,  Thomas M. Shaw ,  David B. Stone

IPC分类号： H01L21/66 ,  G01R31/26 ,  H01L23/522 ,  H01L23/00

CPC分类号： H01L22/34 ,  G01R31/2601 ,  G01R31/2607 ,  H01L23/522 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/13111 ,  H01L2224/14131 ,  H01L2224/14515 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/14

摘要： A method of testing an integrated circuit (IC) chip and a related test structure are disclosed. A test structure includes a monitor chain proximate to at least one solder bump pad, the monitor chain including at least one metal via stack, each metal via stack extending from a lower metal layer in the IC chip to an upper metal layer in the IC chip, such that the monitor chain forms a continuous circuit proximate to the at least one solder bump pad, and where each metal via stack is positioned substantially under the solder bump. A method for testing to detect boundaries of safe effective modulus includes performing a stress test on an IC chip containing the test structure joined to a semiconductor package.

摘要翻译： 公开了一种测试集成电路（IC）芯片和相关测试结构的方法。 测试结构包括靠近至少一个焊料凸块焊盘的监视器链，监视器链包括至少一个金属通孔堆叠，每个金属通孔堆叠从IC芯片中的下金属层延伸到IC芯片中的上金属层 使得监视器链形成靠近至少一个焊料凸块焊盘的连续电路，并且其中每个金属通孔叠层基本位于焊料凸块的下方。 用于检测安全有效模量边界的测试方法包括对包含连接到半导体封装的测试结构的IC芯片执行应力测试。

公开(公告)号：US20140302685A1

公开(公告)日：2014-10-09

申请号：US14307960

申请日：2014-06-18

申请人： International Business Machines Corporation

发明人： Michael P. Belyansky ,  Griselda Bonilla ,  Xiao Hu Liu ,  Son V. Nguyen ,  Thomas M. Shaw ,  Hosadurga K. Shobha ,  Daewon Yang

IPC分类号： H01L21/02

CPC分类号： H01L21/02123 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/318 ,  H01L21/3185 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76834

摘要： A dielectric cap and related methods are disclosed. In one embodiment, the dielectric cap includes a dielectric material having an optical band gap (e.g., greater than about 3.0 electron-Volts) to substantially block ultraviolet radiation during a curing treatment, and including nitrogen with electron donor, double bond electrons. The dielectric cap exhibits a high modulus and is stable under post ULK UV curing treatments for, for example, copper low k back-end-of-line (BEOL) nanoelectronic devices, leading to less film and device cracking and improved reliability.

摘要翻译： 公开了介电盖和相关方法。 在一个实施例中，电介质盖包括具有光学带隙（例如，大于约3.0电子伏特）的电介质材料，以在固化处理期间基本上阻挡紫外线辐射，并且包括氮与电子给体，双键电子。 介电盖表现出高模量，并且在用于例如铜低k后端（BEOL）纳米电子器件的ULK UV固化处理之下是稳定的，导致更少的膜和器件开裂以及改进的可靠性。

公开(公告)号：US08753979B2

公开(公告)日：2014-06-17

申请号：US13838890

申请日：2013-03-15

申请人： International Business Machines Corporation

发明人： Chih-Chao Yang ,  Thomas M. Shaw ,  Keith Kwong Hon Wong ,  Haining S. Yang

IPC分类号： H01L21/00

CPC分类号： H01L21/76841 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53271 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a hybrid interconnect structure including dielectric spacers is provided. The method includes forming at least one opening in a dielectric material utilizing a patterned hard mask located on a surface of the dielectric material as a mask, wherein an undercut is present beneath said patterned hard mask. Next, a dense dielectric spacer is formed in the at least one opening and at least partially on exposed sidewalls of the dielectric material. A diffusion barrier and a conductive material are then formed within the at least one opening.

摘要翻译： 提供一种形成包括电介质间隔物的混合互连结构的方法。 该方法包括使用位于介电材料的表面上的图案化硬掩模作为掩模在电介质材料中形成至少一个开口，其中在所述图案化硬掩模下面存在底切。 接下来，在介电材料的至少一个开口中和至少部分地暴露的侧壁上形成致密的电介质间隔物。 然后在至少一个开口内形成扩散阻挡层和导电材料。

公开(公告)号：US20130230983A1

公开(公告)日：2013-09-05

申请号：US13838890

申请日：2013-03-15

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Chih-Chao Yang ,  Thomas M. Shaw ,  Keith Kwong Hon Wong ,  Haining S. Yang

IPC分类号： H01L21/768

CPC分类号： H01L21/76841 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53271 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a hybrid interconnect structure including dielectric spacers is provided. The method includes forming at least one opening in a dielectric material utilizing a patterned hard mask located on a surface of the dielectric material as a mask, wherein an undercut is present beneath said patterned hard mask. Next, a dense dielectric spacer is formed in the at least one opening and at least partially on exposed sidewalls of the dielectric material. A diffusion barrier and a conductive material are then formed within the at least one opening.

摘要翻译： 提供一种形成包括电介质间隔物的混合互连结构的方法。 该方法包括使用位于介电材料的表面上的图案化硬掩模作为掩模在电介质材料中形成至少一个开口，其中在所述图案化硬掩模下面存在底切。 接下来，在介电材料的至少一个开口中和至少部分地暴露的侧壁上形成致密的电介质间隔物。 然后在至少一个开口内形成扩散阻挡层和导电材料。