公开(公告)号：US20160190313A1

公开(公告)日：2016-06-30

申请号：US14884210

申请日：2015-10-15

申请人： Intel Corporation

发明人： Randy J. Koval ,  Fatma A. Simsek-Ege

IPC分类号： H01L29/78 ,  H01L27/115 ,  H01L29/66

CPC分类号： H01L29/7827 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/7889 ,  H01L29/7926

摘要： A non-volatile memory device and a method for forming the non-volatile memory device are disclosed. The memory device utilizes a local buried channel dielectric in a NAND string that reduces bulk channel leakage at the edge of the NAND string where the electric field gradient along the direction of the string pillar is at or near a maximum during programming operations. The memory device comprises a channel that is coupled at one end to a bitline and at the other end to a source. A select gate is formed at the end of the channel coupled to the bitline to selectively control conduction between the bitline and the channel. At least one non-volatile memory cell is formed along the length of the channel between the select gate and the second end of the channel. A local dielectric region is formed within the channel at the first end of the channel.

摘要翻译： 公开了一种用于形成非易失性存储器件的非易失性存储器件和方法。 存储器件利用NAND串中的局部掩埋沟道电介质，其减小了在NAND串的边缘处的体沟道泄漏，其中在编程操作期间沿串柱方向的电场梯度处于或接近最大值。 存储器件包括一端连接到位线的通道，另一端耦合到源极。 选择栅极形成在耦合到位线的通道的末端，以选择性地控制位线和通道之间的传导。 至少一个非易失性存储单元沿通道的长度在通道的选择栅极和第二端之间形成。 在通道的第一端处的通道内形成局部电介质区域。

公开(公告)号：US09698022B2

公开(公告)日：2017-07-04

申请号：US15207877

申请日：2016-07-12

申请人： Intel Corporation

发明人： Randy J. Koval

IPC分类号： H01L21/336 ,  H01L21/28 ,  H01L29/788 ,  G11C16/04 ,  H01L27/11556 ,  H01L29/78 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/04 ,  H01L29/10 ,  H01L29/16 ,  H01L29/49 ,  H01L27/11524

CPC分类号： H01L21/28273 ,  G11C16/0408 ,  G11C2213/71 ,  H01L21/02148 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/31111 ,  H01L21/32133 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/04 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/4916 ,  H01L29/7827 ,  H01L29/7883 ,  H01L29/7889

摘要： Methods for building a memory device or electronic system may include a memory cell body extending from a substrate, a self-aligned floating gate separated from the memory cell body by a tunneling dielectric film, and a control gate separated from the self-aligned floating gate by a blocking dielectric film. The floating gate is flanked by the memory cell body and the control gate to form a memory cell, and the self-aligned floating gate is at least as thick as the control gate.

公开(公告)号：US09443864B2

公开(公告)日：2016-09-13

申请号：US14835922

申请日：2015-08-26

申请人： Intel Corporation

发明人： Randy J. Koval

IPC分类号： H01L29/788 ,  H01L27/115 ,  G11C16/04 ,  H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/04 ,  H01L29/10 ,  H01L29/16 ,  H01L29/49

CPC分类号： H01L21/28273 ,  G11C16/0408 ,  G11C2213/71 ,  H01L21/02148 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/31111 ,  H01L21/32133 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/04 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/4916 ,  H01L29/7827 ,  H01L29/7883 ,  H01L29/7889

摘要： A memory device or electronic system may include a memory cell body extending from a substrate, a self-aligned floating gate separated from the memory cell body by a tunneling dielectric film, and a control gate separated from the self-aligned floating gate by a blocking dielectric film. The floating gate is flanked by the memory cell body and the control gate to form a memory cell, and the self-aligned floating gate is at least as thick as the control gate. Methods for building such a memory device are also disclosed.

摘要翻译： 存储器件或电子系统可以包括从衬底延伸的存储单元主体，通过隧道电介质膜与存储器单元主体分离的自对准浮动栅极，以及通过阻塞与自对准浮动栅极分离的控制栅极 电介质膜。 浮动栅极侧面是存储单元体和控制栅极，以形成存储单元，并且自对准浮置栅极至少与控制栅极一样厚。 还公开了构建这种存储器件的方法。

公开(公告)号：US09190490B2

公开(公告)日：2015-11-17

申请号：US13832721

申请日：2013-03-15

申请人： Intel Corporation

发明人： Randy J. Koval ,  Fatma A. Simsek-Ege

IPC分类号： H01L29/788 ,  H01L29/66 ,  H01L29/78 ,  H01L29/792 ,  H01L27/115

CPC分类号： H01L29/7827 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/7889 ,  H01L29/7926

摘要： A non-volatile memory device and a method for forming the non-volatile memory device are disclosed. The memory device utilizes a local buried channel dielectric in a NAND string that reduces bulk channel leakage at the edge of the NAND string where the electric field gradient along the direction of the string pillar is at or near a maximum during programming operations. The memory device comprises a channel that is coupled at one end to a bitline and at the other end to a source. A select gate is formed at the end of the channel coupled to the bitline to selectively control conduction between the bitline and the channel. At least one non-volatile memory cell is formed along the length of the channel between the select gate and the second end of the channel. A local dielectric region is formed within the channel at the first end of the channel.

摘要翻译： 公开了一种用于形成非易失性存储器件的非易失性存储器件和方法。 存储器件利用NAND串中的局部掩埋沟道电介质，其减小了在NAND串的边缘处的体沟道泄漏，其中在编程操作期间沿串柱方向的电场梯度处于或接近最大值。 存储器件包括一端连接到位线的通道，另一端耦合到源极。 选择栅极形成在耦合到位线的通道的末端，以选择性地控制位线和通道之间的传导。 至少一个非易失性存储单元沿通道的长度在通道的选择栅极和第二端之间形成。 在通道的第一端处的通道内形成局部电介质区域。

公开(公告)号：US10825831B1

公开(公告)日：2020-11-03

申请号：US16457694

申请日：2019-06-28

申请人： Intel Corporation

发明人： Randy J. Koval ,  Henok T. Mebrahtu ,  Krishna K. Parat

IPC分类号： H01L27/115 ,  H01L29/40 ,  H01L21/02 ,  H01L21/32 ,  H01L27/11582 ,  H01L29/423 ,  H01L27/11556 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/28

摘要： Storage node configurations are described. A storage node (e.g., a floating gate or a charge trap layer of a three-dimensional (3D) NAND flash device) include a channel-facing surface with a radius of curvature. For example, a channel-facing surface of the storage node may be concave. A control gate-facing surface of the storage node may instead, or additionally, also include a radius of curvature. The radius of curvature of the channel-facing and/or control gate-facing surfaces of the storage node is less than or equal to the radius of the channel layer.

公开(公告)号：US09722074B2

公开(公告)日：2017-08-01

申请号：US14884210

申请日：2015-10-15

申请人： Intel Corporation

发明人： Randy J. Koval ,  Fatma A. Simsek-Ege

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157

CPC分类号： H01L29/7827 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/7889 ,  H01L29/7926

摘要： A non-volatile memory device and a method for forming the non-volatile memory device are disclosed. The memory device utilizes a local buried channel dielectric in a NAND string that reduces bulk channel leakage at the edge of the NAND string where the electric field gradient along the direction of the string pillar is at or near a maximum during programming operations. The memory device comprises a channel that is coupled at one end to a bitline and at the other end to a source. A select gate is formed at the end of the channel coupled to the bitline to selectively control conduction between the bitline and the channel. At least one non-volatile memory cell is formed along the length of the channel between the select gate and the second end of the channel. A local dielectric region is formed within the channel at the first end of the channel.

公开(公告)号：US09196625B2

公开(公告)日：2015-11-24

申请号：US14512832

申请日：2014-10-13

申请人： Intel Corporation

发明人： Randy J. Koval

IPC分类号： H01L21/336 ,  H01L29/788 ,  G11C11/34 ,  H01L27/115 ,  G11C16/04 ,  H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/04 ,  H01L29/10 ,  H01L29/16 ,  H01L29/49

CPC分类号： H01L21/28273 ,  G11C16/0408 ,  G11C2213/71 ,  H01L21/02148 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/31111 ,  H01L21/32133 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/04 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/4916 ,  H01L29/7827 ,  H01L29/7883 ,  H01L29/7889

摘要： Methods for building a memory device or electronic system may include a memory cell body extending from a substrate, a self-aligned floating gate separated from the memory cell body by a tunneling dielectric film, and a control gate separated from the self-aligned floating gate by a blocking dielectric film. The floating gate is flanked by the memory cell body and the control gate to form a memory cell, and the self-aligned floating gate is at least as thick as the control gate.

摘要翻译： 用于构建存储器件或电子系统的方法可以包括从衬底延伸的存储器单元主体，通过隧道电介质膜与存储器单元主体分离的自对准浮动栅极以及与自对准浮动栅极分离的控制栅极 通过阻挡电介质膜。 浮动栅极侧面是存储单元体和控制栅极，以形成存储单元，并且自对准浮置栅极至少与控制栅极一样厚。

公开(公告)号：US20150187785A1

公开(公告)日：2015-07-02

申请号：US14512832

申请日：2014-10-13

申请人： INTEL CORPORATION

发明人： Randy J. Koval

IPC分类号： H01L27/115 ,  H01L29/04 ,  H01L29/16 ,  G11C16/04 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/28 ,  H01L21/02 ,  H01L29/49 ,  H01L29/10

CPC分类号： H01L21/28273 ,  G11C16/0408 ,  G11C2213/71 ,  H01L21/02148 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/31111 ,  H01L21/32133 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/04 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/4916 ,  H01L29/7827 ,  H01L29/7883 ,  H01L29/7889

摘要： A memory device or electronic system may include a memory cell body extending from a substrate, a self-aligned floating gate separated from the memory cell body by a tunneling dielectric film, and a control gate separated from the self-aligned floating gate by a blocking dielectric film. The floating gate is flanked by the memory cell body and the control gate to form a memory cell, and the self-aligned floating gate is at least as thick as the control gate. Methods for building such a memory device are also disclosed.

摘要翻译： 存储器件或电子系统可以包括从衬底延伸的存储单元主体，通过隧道电介质膜与存储器单元主体分离的自对准浮动栅极，以及通过阻塞与自对准浮动栅极分离的控制栅极 电介质膜。 浮动栅极侧面是存储单元体和控制栅极，以形成存储单元，并且自对准浮置栅极至少与控制栅极一样厚。 还公开了构建这种存储器件的方法。

公开(公告)号：US10128262B2

公开(公告)日：2018-11-13

申请号：US14998251

申请日：2015-12-26

申请人： INTEL CORPORATION

发明人： Randy J. Koval ,  Hiroyuki Sanda

IPC分类号： H01L27/115 ,  G11C16/26 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157 ,  G11C16/08 ,  H01L27/11526 ,  H01L27/11573 ,  H01L21/3213 ,  H01L27/11519 ,  H01L27/11565

摘要： An apparatus is described having a memory. The memory includes a vertical stack of storage cells, where, a first storage node at a lower layer of the vertical stack has a different structural design than a second storage node at a higher layer of the vertical stack.

公开(公告)号：US20170011928A1

公开(公告)日：2017-01-12

申请号：US15207877

申请日：2016-07-12

申请人： Intel Corporation

发明人： Randy J. Koval

IPC分类号： H01L21/28 ,  H01L27/115 ,  G11C16/04 ,  H01L29/788

CPC分类号： H01L21/28273 ,  G11C16/0408 ,  G11C2213/71 ,  H01L21/02148 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/31111 ,  H01L21/32133 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/04 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/4916 ,  H01L29/7827 ,  H01L29/7883 ,  H01L29/7889

摘要： A memory device or electronic system may include a memory cell body extending from a substrate, a self-aligned floating gate separated from the memory cell body by a tunneling dielectric film, and a control gate separated from the self-aligned floating gate by a blocking dielectric film. The floating gate is flanked by the memory cell body and the control gate to form a memory cell, and the self-aligned floating gate is at least as thick as the control gate. Methods for building such a memory device are also disclosed.

摘要翻译： 存储器件或电子系统可以包括从衬底延伸的存储单元主体，通过隧道电介质膜与存储器单元主体分离的自对准浮动栅极，以及通过阻塞与自对准浮动栅极分离的控制栅极 电介质膜。 浮动栅极侧面是存储单元体和控制栅极，以形成存储单元，并且自对准浮置栅极至少与控制栅极一样厚。 还公开了构建这种存储器件的方法。