公开(公告)号：US09287399B2

公开(公告)日：2016-03-15

申请号：US14508196

申请日：2014-10-07

Applicant: International Business Machines Corporation

Inventor： Bhupesh Chandra ,  Paul Chang ,  Gregory G. Freeman ,  Dechao Guo ,  Judson R. Holt ,  Arvind Kumar ,  Timothy J. McArdle ,  Shreesh Narasimha ,  Viorel Ontalus ,  Sangameshwar Saudari ,  Christopher D. Sheraw ,  Matthew W. Stoker

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/04 ,  H01L29/165 ,  H01L29/36

CPC classification number: H01L29/7848 ,  H01L29/045 ,  H01L29/165 ,  H01L29/36 ,  H01L29/66636 ,  H01L29/7834

Abstract: A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench. A doped semiconductor material is subsequently deposited to fill the source trench and the drain trench. The doped semiconductor material can be deposited such that the facets of the intrinsic buffer semiconductor material are extended and inner sidewalls of the deposited doped semiconductor material merges in each of the source trench and the drain trench. The doped semiconductor material can subsequently grow upward. Faceted intrinsic buffer semiconductor material portions allow greater outdiffusion of dopants near faceted corners while suppressing diffusion of dopants in regions of uniform width, thereby suppressing short channel effects.

公开(公告)号：US09105718B2

公开(公告)日：2015-08-11

申请号：US14224384

申请日：2014-03-25

Applicant: International Business Machines Corporation

Inventor： Jeffrey B. Johnson ,  Shreesh Narasimha ,  Hasan M. Nayfeh ,  Viorel Ontalus ,  Robert R. Robison

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L29/7824 ,  H01L21/76237 ,  H01L21/84 ,  H01L27/1203

Abstract: A structure, a FET, a method of making the structure and of making the FET. The structure including: a silicon layer on a buried oxide (BOX) layer of a silicon-on-insulator substrate; a trench in the silicon layer extending from a top surface of the silicon layer into the silicon layer, the trench not extending to the BOX layer, a doped region in the silicon layer between and abutting the BOX layer and a bottom of the trench, the first doped region doped to a first dopant concentration; a first epitaxial layer, doped to a second dopant concentration, in a bottom of the trench; a second epitaxial layer, doped to a third dopant concentration, on the first epitaxial layer in the trench; and wherein the third dopant concentration is greater than the first and second dopant concentrations and the first dopant concentration is greater than the second dopant concentration.

Abstract translation: 一种结构，一种FET，一种制造该结构和制造该FET的方法。 该结构包括：绝缘体上硅衬底上的掩埋氧化物（BOX）层上的硅层; 所述硅层中的沟槽从所述硅层的顶表面延伸到所述硅层中，所述沟槽不延伸到所述BOX层，所述硅层中的掺杂区域在所述BOX层之间并与所述沟槽的底部邻接， 掺杂到第一掺杂剂浓度的第一掺杂区; 在沟槽的底部掺杂到第二掺杂剂浓度的第一外延层; 在沟槽中的第一外延层上掺杂到第三掺杂剂浓度的第二外延层; 并且其中所述第三掺杂剂浓度大于所述第一和第二掺杂剂浓度，并且所述第一掺杂剂浓度大于所述第二掺杂剂浓度。

公开(公告)号：US09385237B2

公开(公告)日：2016-07-05

申请号：US14687210

申请日：2015-04-15

Applicant: International Business Machines Corporation

Inventor： Pranita Kerber ,  Viorel Ontalus ,  Donald R. Wall ,  Zhengmao Zhu

IPC: H01L29/16 ,  H01L29/786 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/08 ,  H01L29/165 ,  H01L29/417 ,  H01L29/06 ,  H01L29/167 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/823412 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/7834 ,  H01L29/78618 ,  H01L29/78687 ,  H01L2029/7858

Abstract: Carbon-doped semiconductor material portions are formed on a subset of surfaces of underlying semiconductor surfaces contiguously connected to a channel of a field effect transistor. Carbon-doped semiconductor material portions can be formed by selective epitaxy of a carbon-containing semiconductor material layer or by shallow implantation of carbon atoms into surface portions of the underlying semiconductor surfaces. The carbon-doped semiconductor material portions can be deposited as layers and subsequently patterned by etching, or can be formed after formation of disposable masking spacers. Raised source and drain regions are formed on the carbon-doped semiconductor material portions and on physically exposed surfaces of the underlying semiconductor surfaces. The carbon-doped semiconductor material portions locally retard dopant diffusion from the raised source and drain regions into the underlying semiconductor material regions, thereby enabling local tailoring of the dopant profile, and alteration of device parameters for the field effect transistor.

公开(公告)号：US20150084096A1

公开(公告)日：2015-03-26

申请号：US14508196

申请日：2014-10-07

Applicant: International Business Machines Corporation

Inventor： Bhupesh Chandra ,  Paul Chang ,  Gregory G. Freeman ,  Dechao Guo ,  Judson R. Holt ,  Arvind Kumar ,  Timothy J. McArdle ,  Shreesh Narasimha ,  Viorel Ontalus ,  Sangameshwar Saudari ,  Christopher D. Sheraw ,  Matthew W. Stoker

IPC: H01L29/78 ,  H01L29/36

CPC classification number: H01L29/7848 ,  H01L29/045 ,  H01L29/165 ,  H01L29/36 ,  H01L29/66636 ,  H01L29/7834

Abstract: A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench. A doped semiconductor material is subsequently deposited to fill the source trench and the drain trench. The doped semiconductor material can be deposited such that the facets of the intrinsic buffer semiconductor material are extended and inner sidewalls of the deposited doped semiconductor material merges in each of the source trench and the drain trench. The doped semiconductor material can subsequently grow upward. Faceted intrinsic buffer semiconductor material portions allow greater outdiffusion of dopants near faceted corners while suppressing diffusion of dopants in regions of uniform width, thereby suppressing short channel effects.

Abstract translation: 通过选择性外延法将刻面的本征缓冲半导体材料沉积在源沟槽和漏极沟槽的侧壁上。 一个刻面邻接每个边缘，栅极间隔件的外侧壁邻接源沟槽或漏极沟槽的侧壁。 随后沉积掺杂的半导体材料以填充源极沟槽和漏极沟槽。 可以沉积掺杂的半导体材料，使得本征缓冲半导体材料的面被延伸，并且沉积的掺杂半导体材料的内壁在源极沟槽和漏极沟槽的每一个中融合。 掺杂的半导体材料随后可以向上生长。 方面的本征缓冲半导体材料部分允许在均匀宽度的区域中抑制掺杂剂的扩散，从而抑制短沟道效应，从而在小角部附近进一步扩散掺杂剂。

公开(公告)号：US20150221724A1

公开(公告)日：2015-08-06

申请号：US14687210

申请日：2015-04-15

Applicant: International Business Machines Corporation

Inventor： Pranita Kerber ,  Viorel Ontalus ,  Donald R. Wall ,  Zhengmao Zhu

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/417 ,  H01L29/06 ,  H01L29/167

CPC classification number: H01L29/0847 ,  H01L21/823412 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/7834 ,  H01L29/78618 ,  H01L29/78687 ,  H01L2029/7858

Abstract: Carbon-doped semiconductor material portions are formed on a subset of surfaces of underlying semiconductor surfaces contiguously connected to a channel of a field effect transistor. Carbon-doped semiconductor material portions can be formed by selective epitaxy of a carbon-containing semiconductor material layer or by shallow implantation of carbon atoms into surface portions of the underlying semiconductor surfaces. The carbon-doped semiconductor material portions can be deposited as layers and subsequently patterned by etching, or can be formed after formation of disposable masking spacers. Raised source and drain regions are formed on the carbon-doped semiconductor material portions and on physically exposed surfaces of the underlying semiconductor surfaces. The carbon-doped semiconductor material portions locally retard dopant diffusion from the raised source and drain regions into the underlying semiconductor material regions, thereby enabling local tailoring of the dopant profile, and alteration of device parameters for the field effect transistor.

公开(公告)号：US08993395B2

公开(公告)日：2015-03-31

申请号：US13923704

申请日：2013-06-21

Applicant: International Business Machines Corporation

Inventor： Dureseti Chidambarrao ,  Ramachandran Muralidhar ,  Philip J. Oldiges ,  Viorel Ontalus

IPC: H01L21/82 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/84 ,  H01L21/308

CPC classification number: H01L21/823814 ,  H01L21/3086 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823864 ,  H01L21/84

Abstract: A semiconductor structure and method for forming dielectric spacers and epitaxial layers for a complementary metal-oxide-semiconductor field effect transistor (CMOS transistor) are disclosed. Specifically, the structure and method involves forming dielectric spacers that are disposed in trenches and are adjacent to the silicon substrate, which minimizes leakage current. Furthermore, epitaxial layers are deposited to form source and drain regions, wherein the source region and drain regions are spaced at a distance from each other. The epitaxial layers are disposed adjacent to the dielectric spacers and the transistor body regions (i.e., portion of substrate below the gates), which can minimize transistor junction capacitance. Minimizing transistor junction capacitance can enhance the switching speed of the CMOS transistor. Accordingly, the application of dielectric spacers and epitaxial layers to minimize leakage current and transistor junction capacitance in CMOS transistors can enhance the utility and performance of the CMOS transistors in low power applications.

Abstract translation: 公开了用于形成用于互补金属氧化物半导体场效应晶体管（CMOS晶体管）的电介质间隔物和外延层的半导体结构和方法。 具体地，该结构和方法包括形成设置在沟槽中并且与硅衬底相邻的电介质间隔物，这使漏电流最小化。 此外，沉积外延层以形成源极和漏极区域，其中源极区域和漏极区域彼此间隔一定距离。 外延层邻近电介质间隔物和晶体管本体区域（即，栅极下方的衬底部分）设置，这可使晶体管结电容最小化。 最小化晶体管结电容可以提高CMOS晶体管的开关速度。 因此，应用介电间隔物和外延层以最小化CMOS晶体管中的漏电流和晶体管结电容可以增强低功率应用中CMOS晶体管的效用和性能。

公开(公告)号：US20140264558A1

公开(公告)日：2014-09-18

申请号：US13839741

申请日：2013-03-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bhupesh Chandra ,  Paul Chang ,  Gregory G. Freeman ,  Dechao Guo ,  Judson R. Holt ,  Arvind Kumar ,  Timothy J. McArdle ,  Shreesh Narasimha ,  Viorel Ontalus ,  Sangameshwar Rao Saudari ,  Christopher D. Sheraw ,  Matthew W. Stoker

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/045 ,  H01L29/165 ,  H01L29/36 ,  H01L29/66636 ,  H01L29/7834

Abstract: A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench. A doped semiconductor material is subsequently deposited to fill the source trench and the drain trench. The doped semiconductor material can be deposited such that the facets of the intrinsic buffer semiconductor material are extended and inner sidewalls of the deposited doped semiconductor material merges in each of the source trench and the drain trench. The doped semiconductor material can subsequently grow upward. Faceted intrinsic buffer semiconductor material portions allow greater outdiffusion of dopants near faceted corners while suppressing diffusion of dopants in regions of uniform width, thereby suppressing short channel effects.

Abstract translation: 通过选择性外延法将刻面的本征缓冲半导体材料沉积在源沟槽和漏极沟槽的侧壁上。 一个刻面邻接每个边缘，栅极间隔件的外侧壁邻接源沟槽或漏极沟槽的侧壁。 随后沉积掺杂的半导体材料以填充源极沟槽和漏极沟槽。 可以沉积掺杂的半导体材料，使得本征缓冲半导体材料的面被延伸，并且沉积的掺杂半导体材料的内壁在源极沟槽和漏极沟槽的每一个中融合。 掺杂的半导体材料随后可以向上生长。 方面的本征缓冲半导体材料部分允许在均匀宽度的区域中抑制掺杂剂的扩散，从而抑制短沟道效应，从而在小角部附近进一步扩散掺杂剂。

公开(公告)号：US09231108B2

公开(公告)日：2016-01-05

申请号：US14489732

申请日：2014-09-18

Applicant: International Business Machines Corporation

Inventor： Pranita Kerber ,  Viorel Ontalus ,  Donald R. Wall ,  Zhengmao Zhu

IPC: H01L21/8234 ,  H01L29/786 ,  H01L29/66 ,  H01L29/08 ,  H01L29/165 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/823412 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/7834 ,  H01L29/78618 ,  H01L29/78687 ,  H01L2029/7858

Abstract: Carbon-doped semiconductor material portions are formed on a subset of surfaces of underlying semiconductor surfaces contiguously connected to a channel of a field effect transistor. Carbon-doped semiconductor material portions can be formed by selective epitaxy of a carbon-containing semiconductor material layer or by shallow implantation of carbon atoms into surface portions of the underlying semiconductor surfaces. The carbon-doped semiconductor material portions can be deposited as layers and subsequently patterned by etching, or can be formed after formation of disposable masking spacers. Raised source and drain regions are formed on the carbon-doped semiconductor material portions and on physically exposed surfaces of the underlying semiconductor surfaces. The carbon-doped semiconductor material portions locally retard dopant diffusion from the raised source and drain regions into the underlying semiconductor material regions, thereby enabling local tailoring of the dopant profile, and alteration of device parameters for the field effect transistor.

公开(公告)号：US09171844B2

公开(公告)日：2015-10-27

申请号：US14504997

申请日：2014-10-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Unoh Kwon ,  Ramachandran Muralidhar ,  Viorel Ontalus

IPC: H01L21/70 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/423

CPC classification number: H01L27/0922 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/42364

Abstract: A metal gate structure with a channel material and methods of manufacture such structure is provided. The method includes forming dummy gate structures on a substrate. The method further includes forming sidewall structures on sidewalls of the dummy gate structures. The method further includes removing the dummy gate structures to form a first trench and a second trench, defined by the sidewall structures. The method further includes forming a channel material on the substrate in the first trench and in the second trench. The method further includes removing the channel material from the second trench while the first trench is masked. The method further includes filling remaining portions of the first trench and the second trench with gate material.

Abstract translation: 提供了具有通道材料的金属栅极结构及其制造方法。 该方法包括在衬底上形成虚拟栅极结构。 该方法还包括在虚拟栅极结构的侧壁上形成侧壁结构。 该方法还包括去除伪栅极结构以形成由侧壁结构限定的第一沟槽和第二沟槽。 该方法还包括在第一沟槽和第二沟槽中的衬底上形成沟道材料。 该方法还包括在第一沟槽被掩蔽的同时从第二沟槽去除沟道材料。 该方法还包括用栅极材料填充第一沟槽和第二沟槽的剩余部分。

公开(公告)号：US09165944B2

公开(公告)日：2015-10-20

申请号：US14047189

申请日：2013-10-07

Applicant: International Business Machines Corporation

Inventor： Viorel Ontalus ,  Robert R. Robison ,  Xin Wang

IPC: H01L21/336 ,  H01L27/12 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L27/1203 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78609 ,  H01L29/78612 ,  H01L29/78618 ,  H01L29/78621

Abstract: A semiconductor device comprises first and second gate stacks formed on a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes a dielectric layer interposed between a bulk substrate layer and an active semiconductor layer. A first extension implant portion is disposed adjacent to the first gate stack and a second extension implant portion is disposed adjacent to the second gate stack. A halo implant extends continuously about the trench. A butting implant extends between the trench and the dielectric layer. An epitaxial layer is formed at the exposed region such that the butting implant is interposed between the epitaxial layer and the dielectric layer.

Abstract translation: 半导体器件包括形成在绝缘体上半导体（SOI）衬底上的第一和第二栅极叠层。 SOI衬底包括介于主衬底层和有源半导体层之间的电介质层。 第一延伸植入部分邻近第一栅极堆叠设置，并且第二延伸注入部分邻近第二栅极堆叠设置。 晕轮植入物围绕沟槽连续延伸。 对接植入物在沟槽和电介质层之间延伸。 在暴露区域形成外延层，使得对接植入物介于外延层和电介质层之间。