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    Instructions processors, methods, and systems to process secure hash algorithms
    2.
    发明授权
    Instructions processors, methods, and systems to process secure hash algorithms 有权

    公开(公告)号：US10911222B2

    公开(公告)日：2021-02-02

    申请号：US16807021

    申请日：2020-03-02

    Applicant: Intel Corporation

    Inventor： Gilbert M. Wolrich ,  Kirk S. Yap ,  Vinodh Gopal ,  James D. Guilford

    IPC: H04L9/06 ,  G06F21/64 ,  G06F9/30 ,  G06F21/72 ,  G06F21/60

    Abstract: A method of an aspect includes receiving an instruction. The instruction indicates a first source of a first packed data including state data elements ai, bi, ei, and fi for a current round (i) of a secure hash algorithm 2 (SHA2) hash algorithm. The instruction indicates a second source of a second packed data. The first packed data has a width in bits that is less than a combined width in bits of eight state data elements ai, bi, ci, di, ei, fi, gi, hi of the SHA2 hash algorithm. The method also includes storing a result in a destination indicated by the instruction in response to the instruction. The result includes updated state data elements ai+, bi+, ei+, and fi+ that have been updated from the corresponding state data elements ai, bi, ei, and fi by at least one round of the SHA2 hash algorithm.

    Memory controller and methods for memory compression utilizing a hardware compression engine and a dictionary to indicate a zero value, full match, partial match, or no match
    4.
    发明授权
    Memory controller and methods for memory compression utilizing a hardware compression engine and a dictionary to indicate a zero value, full match, partial match, or no match 有权

    公开(公告)号：US10509580B2

    公开(公告)日：2019-12-17

    申请号：US15089456

    申请日：2016-04-01

    Applicant: Intel Corporation

    Inventor： Kirk S. Yap ,  Vinodh Gopal ,  James D. Guilford ,  Sean M. Gulley

    IPC: G06F3/06 ,  G06F12/00 ,  H03M7/30

    Abstract: Methods and apparatuses relating to memory compression and decompression are described, including a memory controller and methods for memory compression utilizing a hardware compression engine and a dictionary to indicate a zero value, full match, partial match, or no match. When indices for multiple sections are the same, an entry in the dictionary may be updated with the value of the section that is most recent, in the same order as in the block of data. In one embodiment, a hardware compression engine is to determine when each section of a plurality of sections of a block of data is a zero value, a full match or a partial match to an entry in a dictionary, or a no match to any entry in the dictionary, encode a tag for each section to indicate the one of the zero value, the full match, the partial match, and the no match, encode a literal when the section is the no match, an index to the entry in the dictionary when the section is the full match, and an index to the entry in the dictionary and non-matching bits when the section is the partial match, and update an entry in the dictionary with a value of a section when the section is the no match, wherein tags for the plurality of sections are to be output from the hardware compression engine in a single field, literals for the plurality of sections are to be output from the hardware compression engine in a single field, indexes for the plurality of sections are to be output from the hardware compression engine in a single field, and non-matching bits for the plurality of sections are to be output from the hardware compression engine in a single field. A hash value may be generated for each of a plurality of sections of a block of data to use as an index in a dictionary.

    METHODS AND APPARATUS TO PARALLELIZE DATA DECOMPRESSION
    5.
    发明申请
    METHODS AND APPARATUS TO PARALLELIZE DATA DECOMPRESSION 审中-公开

    公开(公告)号：US20190363733A1

    公开(公告)日：2019-11-28

    申请号：US16402845

    申请日：2019-05-03

    Applicant: Intel Corporation

    Inventor： Vinodh Gopal ,  James D. Guilford ,  Sudhir K. Satpathy ,  Sanu K. Mathew

    IPC: H03M7/30 ,  H03M7/40

    Abstract: Methods and apparatus to parallelize data decompression are disclosed. An example method selecting initial starting positions in a compressed data bitstream; adjusting a first one of the initial starting positions to determine a first adjusted starting position by decoding the bitstream starting at a training position in the bitstream, the decoding including traversing the bitstream from the training position as though first data located at the training position is a valid token; outputting first decoded data generated by decoding a first segment of the bitstream starting from the first adjusted starting position; and merging the first decoded data with second decoded data generated by decoding a second segment of the bitstream, the decoding of the second segment starting from a second position in the bitstream and being performed in parallel with the decoding of the first segment, and the second segment preceding the first segment in the bitstream.

    Hardware apparatuses and methods for data decompression
    7.
    发明授权
    Hardware apparatuses and methods for data decompression 有权

    公开(公告)号：US10177782B2

    公开(公告)日：2019-01-08

    申请号：US14757854

    申请日：2015-12-26

    Applicant: Intel Corporation

    Inventor： Sudhir K. Satpathy ,  James D. Guilford ,  Sanu K. Mathew ,  Vinodh Gopal ,  Vikram B. Suresh

    IPC: H03M7/30 ,  H03M7/40 ,  G06F9/38 ,  G06F9/46

    Abstract: Methods and apparatuses relating to data decompression are described. In one embodiment, a hardware processor includes a core to execute a thread and offload a decompression thread for an encoded, compressed data stream comprising a literal code, a length code, and a distance code, and a hardware decompression accelerator to execute the decompression thread to selectively provide the encoded, compressed data stream to a first circuit to serially decode the literal code to a literal symbol, serially decode the length code to a length symbol, and serially decode the distance code to a distance symbol, and selectively provide the encoded, compressed data stream to a second circuit to look up the literal symbol for the literal code from a table, look up the length symbol for the length code from the table, and look up the distance symbol for the distance code from the table.

    Method and apparatus for accelerated data compression with hints and filtering
    10.
    发明授权
    Method and apparatus for accelerated data compression with hints and filtering 有权

    公开(公告)号：US09917597B1

    公开(公告)日：2018-03-13

    申请号：US15382031

    申请日：2016-12-16

    Applicant: Intel Corporation

    Inventor： Daniel F. Cutter ,  Vinodh Gopal ,  James D. Guilford

    IPC: H03M7/30 ,  H04L29/06

    CPC classification number: H03M7/3086 ,  H03M7/30 ,  H03M7/6029

    Abstract: A processor includes a decoder to decode an instruction to compress an input data stream and an execution unit for executing the instruction. The execution unit to generate metadata for a current input of the input data stream, the metadata comprises a first hint based on a portion of a current input that represents the input data stream at a current offset, select a first pointer to identify a location in a history buffer in a hash chain, determine whether the metadata generated for the current input matches metadata previously generated for the first pointer, and filter the first pointer from a search for a best match for the current input in the history buffer based on the determination that at least a portion of the metadata for the current input does not match a portion of the metadata for the first pointer.

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