公开(公告)号：US11088263B2

公开(公告)日：2021-08-10

申请号：US16893233

申请日：2020-06-04

申请人： IMEC vzw

发明人： Anabela Veloso ,  Geert Eneman

IPC分类号： H01L29/66 ,  H01L29/16 ,  H01L29/417

摘要： The disclosed technology relates generally to semiconductor processing and more particularly to a method of forming a vertical field-effect transistor device. According to an aspect, a method of forming a vertical field-effect transistor device comprises forming on a substrate a vertical semiconductor structure protruding above the substrate and comprising a lower source/drain portion, an upper source/drain portion and a channel portion arranged between the lower source/drain portion and the upper source/drain portion. The method additionally comprises forming on the channel portion an epitaxial semiconductor stressor layer enclosing the channel portion, wherein the stressor layer and the channel portion are lattice mismatched, forming an insulating layer and a sacrificial structure, wherein the sacrificial structure encloses the channel portion with the stressor layer formed thereon and wherein the insulating layer embeds the semiconductor structure and the sacrificial structure, forming in the insulating layer an opening exposing a surface portion of the sacrificial structure, and etching the sacrificial structure through the opening in the insulating layer, thereby forming a cavity exposing the stressor layer enclosing the channel portion. The method further comprises, subsequent to etching the sacrificial structure, etching the stressor layer in the cavity, and subsequent to etching the stressor layer, forming a gate stack in the cavity, wherein the gate stack encloses the channel portion of the vertical semiconductor structure.

公开(公告)号：US20240178051A1

公开(公告)日：2024-05-30

申请号：US18524355

申请日：2023-11-30

申请人： IMEC VZW

发明人： Anabela Veloso ,  Rongmei Chen ,  An De Keersgieter ,  Geert Eneman ,  Philippe Matagne

IPC分类号： H01L21/74 ,  H01L21/768

CPC分类号： H01L21/743 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76879 ,  H01L21/823431

摘要： A method includes: forming a structure on a frontside of a substrate, the structure including a first and a second source/drain body located in a first and a second source/drain region, respectively, and a channel body including a channel layer extending between the first and second source/drain bodies; forming a trench beside the first source/drain region by etching the substrate such that a lower portion of the trench undercuts the first source/drain region; forming a liner on the trench; forming an opening in the liner underneath the first source/drain region; and forming a dummy interconnect in the trench; where the method further includes exposing the dummy interconnect from a backside of the substrate; removing the dummy interconnect selectively to the liner; and forming a buried interconnect of a conductive material in the trench, where the buried interconnect is connected to the first source/drain body via the opening in the liner.

公开(公告)号：US20210336057A1

公开(公告)日：2021-10-28

申请号：US17241318

申请日：2021-04-27

申请人： IMEC VZW

发明人： Geert Eneman ,  Basoene Briggs ,  An De Keersgieter ,  Anabela Veloso ,  Paola Favia

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/165 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

摘要： A semiconductor structure comprises a semiconductor substrate having a top layer and one or more semiconductor monocrystalline nanostructures. Each nanostructure has a first and a second extremity defining an axis parallel to the top surface of the semiconductor substrate and separated therefrom by a distance, and a source structure epitaxially grown on the first extremity and a drain structure epitaxially grown on the second extremity. The source and drain structures are made of a p-doped (or alternatively n-doped) semiconductor monocrystalline material having a smaller (or alternatively larger) unstrained lattice constant than the unstrained lattice constant of the semiconductor monocrystalline material making the semiconductor monocrystalline nanostructure on which they are grown, thereby creating compressive (or alternatively tensile) strain in that semiconductor monocrystalline nanostructure.

公开(公告)号：US20170033183A1

公开(公告)日：2017-02-02

申请号：US15218922

申请日：2016-07-25

申请人： IMEC VZW

发明人： Bernardette Kunert ,  Robert Langer ,  Geert Eneman

IPC分类号： H01L29/10 ,  H01L29/04 ,  H01L29/161 ,  H01L21/306 ,  H01L21/02 ,  H01L29/423 ,  H01L21/324

CPC分类号： H01L29/1054 ,  H01L21/02381 ,  H01L21/02455 ,  H01L21/02469 ,  H01L21/02513 ,  H01L21/02524 ,  H01L21/02532 ,  H01L21/30612 ,  H01L21/3245 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/42356 ,  H01L29/775

摘要： Disclosed herein is a semiconductor structure including: (i) a monocrystalline substrate having a top surface, (ii) a non-crystalline structure overlying the monocrystalline substrate and including an opening having a width smaller than 10 microns and exposing part of the top surface of the monocrystalline substrate. The semiconductor structure also includes (iii) a buffer structure having a bottom surface abutting the part and a top surface having less than 108 threading dislocations per cm2, the buffer structure being made of a material having a first lattice constant. The semiconductor structure also includes (iv) one or more group IV monocrystalline structures abutting the buffer structure and that are made of a material having a second lattice constant, different from the first lattice constant.

摘要翻译： 本文公开了一种半导体结构，其包括：（i）具有顶表面的单晶衬底，（ii）覆盖在单晶衬底上的非晶体结构，并且包括具有小于10微米的宽度的开口，并暴露部分顶部表面的 单晶衬底。 半导体结构还包括（iii）具有邻接部分的底表面的缓冲结构和每平方厘米具有小于108个穿透位错的顶表面，该缓冲结构由具有第一晶格常数的材料制成。 半导体结构还包括（iv）邻接缓冲结构的一个或多个IV族单晶结构，并且由具有与第一晶格常数不同的第二晶格常数的材料制成。

公开(公告)号：US11387350B2

公开(公告)日：2022-07-12

申请号：US16719852

申请日：2019-12-18

申请人： IMEC vzw

发明人： Geert Eneman ,  Bartlomiej Pawlak ,  Liesbeth Witters ,  Geoffrey Pourtois

IPC分类号： H01L29/66 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/161 ,  H01L29/78

摘要： According to one aspect, a method of fabricating a semiconductor structure includes cutting a semiconductor fin extending along a substrate. Cutting the semiconductor fin can comprise forming a fin cut mask. The fin cut mask can define a number of masked regions and a number of cut regions. The method can include cutting the fin into a number of fin parts by etching the fin in the cut regions. The method can further comprise forming an epitaxial semiconductor capping layer on the fin prior to forming the fin cut mask or on the fin parts subsequent to cutting the fin. A capping layer material and a fin material can be lattice mismatched. According to another aspect, a corresponding semiconductor structure comprises fin parts.

公开(公告)号：US20200083116A1

公开(公告)日：2020-03-12

申请号：US16567485

申请日：2019-09-11

申请人： IMEC VZW

发明人： Steven Demuynck ,  Geert Eneman ,  Vladimir Machkaoutsan

IPC分类号： H01L21/8238 ,  H01L27/11 ,  H01L27/092 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20 ,  H01L29/78 ,  H01L23/535 ,  H01L29/66

摘要： A method of forming gate contacts and/or contact lines on a plurality of fins. The method comprises providing a wafer comprising a semiconductor structure which comprises a plurality of fins. The method further comprises patterning at least one continuous trench over the fins, and filling at least one of the trenches with metal to obtain at least one continuous gate in contact with the fins and/or filling at least one of the trenches with metal to obtain at least one continuous contact line in contact with the fins. The method further comprises cutting the metal of the at least one gate and/or cutting the metal of the at least one contact line in between some of the fins.

公开(公告)号：US20190172913A1

公开(公告)日：2019-06-06

申请号：US16171627

申请日：2018-10-26

申请人： IMEC VZW

发明人： Hu Liang ,  Xiuju Zhou ,  Geert Eneman

IPC分类号： H01L29/20 ,  H01L29/778 ,  H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L33/32 ,  H01L33/00 ,  H01L29/04 ,  H01L21/02

摘要： A semiconductor structure and a method for forming the semiconductor structure are provided. The method includes: providing a monocrystalline substrate having an upper surface covered with a masking layer comprising at least one opening exposing the upper surface; filling the opening by epitaxially growing therein a first layer comprising a first Group III-nitride compound; and growing the first layer further above the opening and on the masking layer by epitaxial lateral overgrowth, wherein the at least one opening has a top surface defined by three or more straight edges forming a polygon parallel to the upper surface and oriented in such a way with respect to the crystal lattice of the monocrystalline substrate so as to permit the epitaxial lateral overgrowth of the first layer in a direction perpendicular to at least one of the edges, thereby forming the semiconductor structure as an elongated structure.

公开(公告)号：US09698262B2

公开(公告)日：2017-07-04

申请号：US15072130

申请日：2016-03-16

申请人： IMEC VZW ,  GLOBALFOUNDRIES INC.

发明人： Bartlomiej Pawlak ,  Geert Eneman

IPC分类号： H01L29/74 ,  H01L29/80 ,  H01L29/94 ,  H01L21/00 ,  H01L21/338 ,  H01L21/337 ,  H01L29/78 ,  H01L21/765 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423

CPC分类号： H01L29/7827 ,  H01L21/76 ,  H01L21/765 ,  H01L29/0607 ,  H01L29/0657 ,  H01L29/1083 ,  H01L29/42356

摘要： A vertical FinFET semiconductor device and a method of forming the same are disclosed. In one aspect, the semiconductor device includes a current-blocking structure formed over a semiconductor structure and a semiconductor fin formed on the current-blocking structure. The current blocking structure includes a first layer of a first conductive type, a layer of a second conductive type over the first layer, and a second layer of the first conductive type over the layer of the second conductive type. The semiconductor fin has a doped bottom portion contacting the current-blocking structure, a doped top portion formed vertically opposite to the doped bottom portion and a channel portion vertically interposed between the doped bottom portion and the doped top portion.

公开(公告)号：US20160027876A1

公开(公告)日：2016-01-28

申请号：US14709696

申请日：2015-05-12

申请人： IMEC VZW ,  SAMSUNG ELECTRONICS CO. LTD.

发明人： Seung Hun Lee ,  Geert Eneman

IPC分类号： H01L29/10 ,  H01L29/417 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/41783 ,  H01L29/7848 ,  H01L29/7849

摘要： A CMOS semiconductor FinFET device and a method for manufacturing a CMOS semiconductor FinFET device are disclosed. The device may comprise an nFinFET and a pFinFET having a channel region comprising Ge on a common strain-relaxed buffer layer comprising SiGe. The concentration of Ge in the channel regions is higher than the concentration of Ge in the strain-relaxed buffer layer. The device further comprises a source/drain region for the nFinFET, the source/drain region comprising SiGe; and a source/drain region for the pFinFET, the second source/drain region comprising Ge.

摘要翻译： 公开了CMOS半导体FinFET器件和用于制造CMOS半导体FinFET器件的方法。 器件可以包括在包含SiGe的公共应变松弛缓冲层上具有包含Ge的沟道区的nFinFET和pFinFET。 通道区中Ge的浓度高于应变松弛缓冲层中Ge的浓度。 器件还包括用于nFinFET的源极/漏极区域，源极/漏极区域包括SiGe; 以及用于pFinFET的源极/漏极区域，第二源极/漏极区域包括Ge。

公开(公告)号：US20190081156A1

公开(公告)日：2019-03-14

申请号：US16119132

申请日：2018-08-31

申请人： IMEC VZW

发明人： Anabela Veloso ,  Geert Eneman ,  Nadine Collaert ,  Erik Rosseel

IPC分类号： H01L29/66 ,  H01L29/10 ,  H01L29/423 ,  H01L21/02 ,  H01L21/306 ,  H01L29/78 ,  H01L29/165 ,  H01L29/08

摘要： A device and method for forming a vertical channel device is disclosed. The method includes: forming a vertical semiconductor pillar on a substrate, the vertical semiconductor pillar including a first pillar section, a second pillar section and a third pillar section, wherein the second pillar section is arranged between the first pillar section and the third pillar section and wherein the second pillar section is formed of a material being different from a material forming an upper portion of the first pillar section and different from a material forming a lower portion of the third pillar section; forming a spacer layer on a peripheral surface of the upper portion of the first pillar section and on a peripheral surface of the lower portion of the third pillar section; and forming a gate stack embedding the second pillar section and said upper portion of the first pillar section and said lower portion of the third pillar section, wherein the spacer layer forms a spacer between the gate stack and said upper portion of the first pillar section and between the gate stack and said lower portion of the third pillar section.