公开(公告)号：US06902660B2

公开(公告)日：2005-06-07

申请号：US10231052

申请日：2002-08-30

Applicant: Hyuek Jae Lee ,  Jin Yu

Inventor： Hyuek Jae Lee ,  Jin Yu

IPC: H05K3/00 ,  C25D5/02 ,  H05K3/20 ,  H05K3/38 ,  H05K3/42 ,  H05K3/46 ,  C25D1/00

CPC classification number: H05K3/4617 ,  C25D5/02 ,  H05K3/205 ,  H05K3/384 ,  H05K3/423 ,  H05K2201/0154 ,  H05K2203/0733

Abstract: Disclosed is a fabrication method of a printed circuit board, consisting of plating a metal on a pattern-formed metallic substrate to form a conductive metal line; forming a polymer layer as a base substrate over the conductive metal line-formed metallic substrate and drying the formed polymer layer; forming a via hole in the polymer layer, followed by plugging the formed via hole by electroplating; and removing the metallic substrate. The method is advantageous in terms of maximum efficiency of use of the surface area of PCB, and fineness and high integration of circuits because of not requiring an additional etching process.

Abstract translation: 公开了一种印刷电路板的制造方法，其包括在图案形成的金属基板上镀金属以形成导电金属线; 在导电金属线形金属基材上形成聚合物层作为基底，干燥所形成的聚合物层; 在聚合物层中形成通孔，然后通过电镀将形成的通孔堵塞; 并去除金属基底。 该方法在PCB的表面积的最大使用效率以及电路的细度和高集成度方面是有利的，因为不需要另外的蚀刻工艺。

公开(公告)号：USD838859S1

公开(公告)日：2019-01-22

申请号：US29618205

申请日：2017-09-20

Applicant: Jin Yu

Designer： Jin Yu

公开(公告)号：US20100240174A1

公开(公告)日：2010-09-23

申请号：US12680760

申请日：2007-12-04

Applicant: Jin Yu ,  Young-Kun Jee

Inventor： Jin Yu ,  Young-Kun Jee

IPC: H01L21/768 ,  H01L21/50

CPC classification number: H01L21/768 ,  H01L21/76898 ,  H01L24/11 ,  H01L24/12 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/00

Abstract: Disclosed are via, a method for formation of via using zinc and zinc alloys, and a process for fabrication of three-dimensional multiple chip stack packages by using the same. In lamination of three-dimensional chips, the chips with reduced defects are rapidly formed by the steps of: punching each of the chips to form a via hole used for a circuit wiring between the chips; depositing a seed layer on an inside of the via hole; forming a plated layer inside the via hole by using Zn and Zn alloys through an electroplating process; removing oxide film from surface of the plated layer; and heat treating the via hole at a temperature of more than melting point of the Zn and Zn alloys. Particularly, the chip having Zn via formed according to the present invention has an advantage of simultaneously overcoming problems in establishment of processing parameters caused by Cu via (e.g., plating mode, current density, influence of additives, pore formation, etc.), problems in successive processes caused by Sn (and other low melting point metals) via (e.g., soldering, chip stack, etc.) and difficulty in mechanical reliability of the process. Additionally, when stacking multiple chips with various functions in the three-dimensional chip stack package, the package can be simply fabricated by controlling contents of constitutional elements in Zn alloy via which has specific thermal properties (such as melting point, thermal expansion coefficient, etc.) suitable for processing temperature of each of the chips.

Abstract translation: 公开了通过使用锌和锌合金形成通孔的方法，以及使用该方法制造三维多芯片堆叠封装的方法。 在三维芯片的层叠中，通过以下步骤快速形成具有减少的缺陷的芯片：冲压每个芯片以形成用于芯片之间的电路布线的通孔; 在所述通孔的内部沉积种子层; 通过使用Zn和Zn合金通过电镀工艺在通孔内形成镀层; 从镀层的表面去除氧化膜; 并在Zn和Zn合金的熔点以上的温度下对通孔进行热处理。 特别地，具有根据本发明形成的Zn通孔的芯片具有同时克服由Cu通孔（例如电镀模式，电流密度，添加剂的影响，孔形成等）引起的加工参数建立中的问题的优点，问题 在由Sn（和其他低熔点金属）经由（例如，焊接，芯片堆叠等）引起的连续工艺中以及该工艺的机械可靠性困难。 此外，当在三维芯片堆叠封装中堆叠具有各种功能的多个芯片时，可以通过控制具有特定热性能（如熔点，热膨胀系数等）的Zn合金中的组成元素的内容物来简单地制造封装 。）适合每个芯片的处理温度。

公开(公告)号：US20090202241A1

公开(公告)日：2009-08-13

申请号：US12367406

申请日：2009-02-06

Applicant: Jin Yu ,  Randy K. Schwarz

Inventor： Jin Yu ,  Randy K. Schwarz

IPC: H04J14/00

CPC classification number: H04J3/1694 ,  H04B10/27 ,  H04J14/0226 ,  H04J14/0238 ,  H04J14/0252 ,  H04J14/0279 ,  H04J14/028 ,  H04J14/0282 ,  H04J14/0283 ,  H04J14/0284 ,  H04J2203/0067

Abstract: An optical distribution system for vehicle information systems installed aboard passenger vehicles, such as automobiles and aircraft, and methods for manufacturing and using same. Each system resource of the vehicle information system couples with the optical distribution system via an optical transceiver system. The optical transceiver systems provide a link interface between the system resources and the optical distribution system for supporting the transmission and reception of optical communication signals among the system resources via the optical distribution system. The optical distribution system couples the system resources via fiber optic communication connections that can support high data transfer rates. Being light weight, compact, and requiring little, if any, electrical power, the optical distribution system advantageously supports full communications among the system resources of the vehicle information system, while reducing the costs of operating and transporting the vehicle information system aboard the passenger vehicle.

Abstract translation: 用于车载信息系统的光分配系统，其安装在诸如汽车和飞机的客车上，以及制造和使用它们的方法。 车辆信息系统的每个系统资源经由光收发器系统与光分配系统耦合。 光收发器系统在系统资源和光分配系统之间提供链路接口，用于经由光分配系统支持系统资源之间的光通信信号的发送和接收。 光分配系统通过可支持高数据传输速率的光纤通信连接来耦合系统资源。 光分配系统的重量轻，紧凑，并且需要很少（如果有的话）电力，有利地支持车辆信息系统的系统资源之间的完全通信，同时降低在乘客车辆上操作和运输车辆信息系统的成本 。

公开(公告)号：US20070298620A1

公开(公告)日：2007-12-27

申请号：US11309142

申请日：2006-06-27

Applicant: Kuang-Yeh Chang ,  Jin Yu

Inventor： Kuang-Yeh Chang ,  Jin Yu

IPC: H01L21/31

CPC classification number: H01L24/02 ,  H01L22/14 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/3025

Abstract: A storage structure for a microelectronic device including a chip which has completed all back-end-of-line (BEOL) processes and a solvent dissolvable polymer layer covering the surface of the chip. Since the surface of the chip is isolated from the external environment by the solvent dissolvable polymer layer, corrosion, discoloring or delamination of the chip can be avoided.

Abstract translation: 一种微电子器件的存储结构，包括已经完成了所有后端（BEOL）工艺的芯片和覆盖芯片表面的溶剂可溶性聚合物层。 由于芯片的表面通过溶剂可溶性聚合物层与外部环境隔离，因此可以避免芯片的腐蚀，变色或分层。

公开(公告)号：US20060285460A1

公开(公告)日：2006-12-21

申请号：US11370881

申请日：2006-03-09

Applicant: Jin Yu ,  Otsuka Tatsuhiro ,  Jong Ko ,  Ji Baek

Inventor： Jin Yu ,  Otsuka Tatsuhiro ,  Jong Ko ,  Ji Baek

IPC: G11B20/10 ,  G11B7/12

CPC classification number: G11B20/1217 ,  G11B7/00736 ,  G11B7/1267 ,  G11B2020/1275 ,  G11B2020/1297 ,  G11B2220/216

Abstract: A method of managing optimum power control (OPC) data in a lead-in zone of a rewritable high-density optical disc, wherein an OPC back data zone is allocated in the lead-in zone of the rewritable high-density optical disc and OPC data is written in the OPC back data zone so that a subsequent OPC process can be immediately performed based on the written OPC data. The method includes allocating a specified zone used in performing an OPC process within the lead-in zone of the rewritable high-density optical disc, writing OPC data for the OPC process in the specified zone, reading the OPC data written in the specified zone, and performing the OPC process based on the read OPC data.

Abstract translation: 一种在可重写高密度光盘的导入区域中管理最佳功率控制（OPC）数据的方法，其中OPC可重写数据区被分配在可重写高密度光盘和OPC的导入区中 将数据写入OPC back数据区，以便可以基于写入的OPC数据立即执行后续OPC过程。 该方法包括在可重写高密度光盘的导入区中分配用于执行OPC处理的指定区域，在指定区域中写入用于OPC处理的OPC数据，读取写入指定区域中的OPC数据， 并根据读取的OPC数据执行OPC过程。

公开(公告)号：US09408556B2

公开(公告)日：2016-08-09

申请号：US13990007

申请日：2010-12-01

Applicant: Ping Wang ,  Di Wang ,  Le Wang ,  Jin Yu ,  Kai Yu ,  Yishan Wang ,  Lin Wang ,  Cong Zhao

Inventor： Ping Wang ,  Di Wang ,  Le Wang ,  Jin Yu ,  Kai Yu ,  Yishan Wang ,  Lin Wang ,  Cong Zhao

IPC: A61B5/08 ,  G01N33/00 ,  G01N33/497 ,  A61B5/097

CPC classification number: A61B5/082 ,  A61B5/097 ,  G01N33/0047 ,  G01N33/497

Abstract: The present embodiments disclose a device including a module for sampling, separating and enriching a detected object, an exhaled breath condensates (EBCs) detection module and a combined volatile organic compounds (VOCs) detection module. The sampling module is connected with the EBCs detection module via a syringe pump for sample injection and is connected with the combined VOCs detection module by a capillary separation column. EBCs and VOCs in human exhaled breath are simultaneously sampled, separated and condensed; the heavy metal ions, cell factors, etc. in the collected EBCs are detected with a light addressable potentiometric sensor (LAPS); the condensed VOCs can be quantitatively detected by the combined VOCs detection module with a high sensitivity; and a heating rod and a platinum resistor can be conveniently replaced because a separated outlet heating piece is designed in the combined VOCs detection module.

Abstract translation: 本实施例公开了一种包括用于对检测到的物体进行取样，分离和富集的模块，呼出呼吸冷凝物（EBC）检测模块和组合的挥发性有机化合物（VOC））检测模块的装置。 采样模块通过注射泵与EBC检测模块连接，用于注射样品，并通过毛细管分离柱与组合的VOC检测模块连接。 人呼吸中的EBC和VOCs被同时取样，分离和浓缩; 用光寻址电位传感器（LAPS）检测收集的EBC中的重金属离子，细胞因子等; 可以通过组合的VOC检测模块以高灵敏度定量检测浓缩的VOC; 并且可以方便地更换加热棒和铂电阻器，因为在组合的VOC检测模块中设计了分离的出口加热片。

公开(公告)号：US20070220458A1

公开(公告)日：2007-09-20

申请号：US11308343

申请日：2006-03-17

Applicant: Wen-Zhan Zhou ,  Jin Yu ,  Kai-Hung Alex See

Inventor： Wen-Zhan Zhou ,  Jin Yu ,  Kai-Hung Alex See

IPC: G06F17/50

CPC classification number: G03F7/70625 ,  G03F7/70508 ,  H01L22/26 ,  H01L22/34

Abstract: A method for detecting semiconductor-manufacturing conditions includes providing a photomask with a plurality of pattern areas each having a plurality of test lines with different pitches, exposing a plurality of wafer with the photomask in different manufacturing conditions, measuring the critical dimensions of the plurality of pattern areas, generating a library of relationships between the pitches and the critical dimension of the pattern areas, exposing a test wafer in an unknown manufacturing condition, finding out a relationships between the pitches and the critical dimension of the pattern areas of the test wafer, searching for a most similar relationship in the library, and detecting a set of manufacturing parameters used to expose the test wafer.

Abstract translation: 一种用于检测半导体制造条件的方法包括提供具有多个图案区域的光掩模，每个图案区域具有多个具有不同间距的测试线，在不同制造条件下用光掩模曝光多个晶片，测量多个 产生间距和图案区域的关键尺寸之间的关系库，使未知制造条件下的测试晶片暴露出来，找出测试晶片的图案区域的间距与临界尺寸之间的关系， 在库中搜索最相似的关系，并且检测用于暴露测试晶片的一组制造参数。

公开(公告)号：US20070167110A1

公开(公告)日：2007-07-19

申请号：US11306913

申请日：2006-01-16

Applicant: Yu-Hsiang Tseng ,  Kai-Hung Alex See ,  Mei-Sheng Zhou ,  Jin Yu ,  Zheng Zou ,  Wen-Zhan Zhou

Inventor： Yu-Hsiang Tseng ,  Kai-Hung Alex See ,  Mei-Sheng Zhou ,  Jin Yu ,  Zheng Zou ,  Wen-Zhan Zhou

IPC: B24B51/00

CPC classification number: B24B37/30

Abstract: A multi-zone carrier head includes a housing; a retaining ring secured to a lower edge of the housing; a backing plate having a plurality of non-concentric pressure zones defined by a plurality of isolated apertures on the backing plate; wherein the backing plate has a wafer side and a non-wafer side, the wafer side facing a backside of a wafer during a CMP operation; and a plurality of pneumatic bladder for independently controlling pressure exerted in the respective non-concentric pressure zones on the backside of the wafer during the CMP operation.

Abstract translation: 多区域承载头包括壳体; 保持环固定到壳体的下边缘; 背板，其具有由背板上的多个隔离孔限定的多个非同心压力区; 其中所述背板具有晶片侧和非晶片侧，所述晶片侧在CMP操作期间面向晶片的背面; 以及多个气囊，用于在CMP操作期间独立地控制施加在晶片背面上的各个非同心压力区中的压力。

公开(公告)号：US20070158391A1

公开(公告)日：2007-07-12

申请号：US11590249

申请日：2006-10-30

Applicant: Yoon-Chul Son ,  Jong-Yeon Kim ,  Jin Yu

Inventor： Yoon-Chul Son ,  Jong-Yeon Kim ,  Jin Yu

IPC: A47J36/02

CPC classification number: H01L24/10 ,  B23K35/262 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/13 ,  H01L2224/13139 ,  H01L2224/16 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H05K3/244 ,  H05K3/3463 ,  H05K2203/072 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00

Abstract: The present invention relates, generally, to methods for joining an electronic part finished with nickel and an electronic part finished with electroless nickel, which can prevent a brittle fracture, more particularly, to a method for joining an electronic part finished with nickel and an electronic part finished with electroless nickel with a solder by controlling the composition of the solder to prevent a brittle fracture occurring at the solder joining portion.A method for joining an electronic part finished with nickel and an electronic part finished with electroless nickel, comprising: (1) reflowing solder to a nickel portion of an electronic part finished with nickel to obtain an electronic part where an intermetallic compound and a solder are formed; (2) obtaining an electronic part finished with an eletroless nickel, of which the nickel portion is connected with the solder; and (3) solder-joining an electronic part finished with nickel obtained in the step (1) and the electronic part finished with electroless nickel obtained in the step (2).

Abstract translation: 本发明一般地涉及将镍完成的电子部件和能够防止脆性断裂的化学镀镍的电子部件接合的方法，更具体地说，涉及一种用镍和电子制成的电子部件的接合方法 通过控制焊料的组成来防止在焊料接合部分发生脆性断裂，通过焊料完成无电镀镍。 一种将镍完成的电子部件和用非电解镍完成的电子部件的接合方法，其特征在于，包括：（1）将焊料回流到镍完成的电子零件的镍部分，得到金属间化合物和焊料的电子部件 形成 （2）获得用无电镍完成的电子部件，其中镍部分与焊料连接; 和（3）将步骤（1）中得到的镍完成的电子部件与在步骤（2）中获得的化学镀镍的电子部件进行焊接接合。