公开(公告)号：US07741196B2

公开(公告)日：2010-06-22

申请号：US11668453

申请日：2007-01-29

申请人： Heng Keong Yip ,  Wai Yew Lo ,  Lan Chu Tan

发明人： Heng Keong Yip ,  Wai Yew Lo ,  Lan Chu Tan

IPC分类号： H01L21/30

CPC分类号： H01L21/3043 ,  H01L21/02118 ,  H01L21/312 ,  H01L21/78 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor wafer for dicing includes providing a semiconductor wafer including a substrate and a plurality of upper layers on the substrate that form a formation of die areas. The formation is arranged so that adjacent die areas are separated by a path for a dicing tool. Within each path, a pair of spaced apart lines is fabricated. Each line defines a dicing edge of a respective path and has at least one trench extending between a top surface of the wafer and the substrate. Each trench is filled with a stress absorbing material for reducing die tool induced stress on the die areas during dicing.

摘要翻译： 制造用于切割的半导体晶片的方法包括在基板上提供包括基板和多个上层的半导体晶片，形成管芯区域的形成。 该结构布置成使得相邻的模具区域被用于切割工具的路径分开。 在每个路径中，制造一对间隔开的线。 每条线限定相应路径的切割边缘，并且具有在晶片的顶表面和基底之间延伸的至少一个沟槽。 每个沟槽填充有应力吸收材料，用于在切割期间减少模具区域上的模具工具引起的应力。

公开(公告)号：US20080179710A1

公开(公告)日：2008-07-31

申请号：US11668453

申请日：2007-01-29

申请人： Heng Keong Yip ,  Wai Yew Lo ,  Lan Chu Tan

发明人： Heng Keong Yip ,  Wai Yew Lo ,  Lan Chu Tan

IPC分类号： H01L23/544 ,  H01L21/76

CPC分类号： H01L21/3043 ,  H01L21/02118 ,  H01L21/312 ,  H01L21/78 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor wafer for dicing includes providing a semiconductor wafer including a substrate and a plurality of upper layers on the substrate that form a formation of die areas. The formation is arranged so that adjacent die areas are separated by a path for a dicing tool within each path, a pair of spaced apart lines is fabricated. Each line defines a dicing edge of a respective path and has at least one trench extending between a top surface of the wafer and the substrate. Each trench is filled with a stress absorbing material for reducing die tool induced stress on the die areas during dicing.

摘要翻译： 制造用于切割的半导体晶片的方法包括在基板上提供包括基板和多个上层的半导体晶片，形成管芯区域的形成。 该组合被布置成使得相邻的模具区域被用于每个路径内的切割工具的路径分开，制造一对间隔开的线。 每条线限定相应路径的切割边缘，并且具有在晶片的顶表面和基底之间延伸的至少一个沟槽。 每个沟槽填充有应力吸收材料，用于在切割期间减少模具区域上的模具工具引起的应力。

公开(公告)号：US07473586B1

公开(公告)日：2009-01-06

申请号：US11849301

申请日：2007-09-03

申请人： Wai Yew Lo ,  Heng Keong Yip

发明人： Wai Yew Lo ,  Heng Keong Yip

IPC分类号： H01L21/00

CPC分类号： H01L21/4846 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/81001 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01055 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A flip-chip bump carrier type package is formed by providing a sheet of metal foil and forming cavities in a first surface of the sheet. The cavities are plated with a conductive metal to form external interconnects. An insulating film is formed over the metal foil first surface and the plated cavities and then vias are formed in the insulating film. The vias contact respective ones of the plated cavities. The vias are then plated and a solder resist film is formed over the insulating film and the plated vias. The solder resist film is processed to form exposed areas above the vias, which areas are then plated with a conductive metal. A bumped semiconductor die is attached to the first surface of the metal foil, where the die bumps contact respective ones of the plated, exposed areas, which electrically connects the die to the plated cavities. Finally, the sheet of metal foil is removed so that outer surfaces of the plated cavities are exposed. As stated above, the plated cavity outer surfaces form electrical interconnects between the die and a printed wiring board.

摘要翻译： 通过在片材的第一表面中提供金属箔片和形成空腔来形成倒装芯片凸块载体型封装。 空腔用导电金属镀以形成外部互连。 在金属箔第一表面和电镀腔上形成绝缘膜，然后在绝缘膜中形成通孔。 通孔接触相应的电镀腔。 然后对通孔进行电镀，并且在绝缘膜和电镀通孔上形成阻焊膜。 处理阻焊膜以形成通孔上方的暴露区域，然后用导电金属镀覆该区域。 撞击的半导体管芯附着到金属箔的第一表面上，其中管芯凸块接触电镀的暴露区域中的相应电极，该裸露区域将管芯电连接到电镀腔。 最后，去除金属箔片，使得电镀腔的外表面露出。 如上所述，电镀腔体外表面在模具和印刷线路板之间形成电互连。

公开(公告)号：US20090152717A1

公开(公告)日：2009-06-18

申请号：US11957486

申请日：2007-12-17

申请人： Wai Yew Lo ,  Heng Keong Yip

发明人： Wai Yew Lo ,  Heng Keong Yip

IPC分类号： H01L23/488 ,  H01L21/56

CPC分类号： H01L21/6835 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/85001 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/0665 ,  H01L2224/92247 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of packaging semiconductor integrated circuits, including the steps of providing a transfer film and forming a patterned, conductive layer on a surface of the transfer film. A first semiconductor integrated circuit (IC) then is attached to the transfer film, where an active side of the first IC is attached to the transfer film. A second semiconductor IC then is attached to the first IC, where a bottom side of the second IC is attached to a bottom side of the first IC. Die pads on an active surface of the second IC are electrically connected to the conductive layer with wires and then a resin material is provided on one side of the transfer film to encapsulate the first and second ICs, the wires and a portion of the conductive layer. Next the transfer film is removed, which exposes the active side of the first IC and the conductive layer. An electrical distribution layer is formed over the active side of the first IC and the conductive layer and conductive balls are attached to the electrical distribution layer. The conductive balls allow electrical interconnection to the first and second integrated circuits.

摘要翻译： 一种封装半导体集成电路的方法，包括以下步骤：在转印膜的表面上提供转印膜并形成图案化的导电层。 然后，第一半导体集成电路（IC）附接到转印膜，其中第一IC的有源侧附着到转印膜上。 然后，第二半导体IC被附接到第一IC，其中第二IC的底侧附接到第一IC的底侧。 第二IC的有源表面上的焊盘与导体层电连接，然后在转移膜的一侧上设置树脂材料，以封装第一和第二IC，导线和一部分导电层 。 接下来，去除转印膜，其暴露第一IC和导电层的活性侧。 在第一IC的有源侧上形成配电层，导电层和导电球附着在配电层上。 导电球允许与第一和第二集成电路的电互连。

公开(公告)号：US07531383B2

公开(公告)日：2009-05-12

申请号：US11554920

申请日：2006-10-31

申请人： Wai Yew Lo ,  Heng Keong Yip

发明人： Wai Yew Lo ,  Heng Keong Yip

IPC分类号： H01L21/00

CPC分类号： H01L21/568 ,  H01L21/561 ,  H01L23/3107 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An array QFN package (10) includes a first semiconductor package (12) and a lead frame (14) having a plurality of leads (16). A first IC die (22) is attached on a first side to the first semiconductor package (12) and is electrically connected to the leads (16) of the lead frame (14). A mold compound (30) encapsulates the first IC die (22), a portion of the first semiconductor package (12) and a portion of the leads (16) such that a plurality of I/O terminals (32) on the semiconductor package (10) is exposed.

摘要翻译： 阵列QFN封装（10）包括具有多个引线（16）的第一半导体封装（12）和引线框架（14）。 第一IC芯片（22）在第一侧附接到第一半导体封装（12）并且电连接到引线框架（14）的引线（16）。 模具化合物（30）封装第一IC管芯（22），第一半导体封装（12）的一部分和引线（16）的一部分，使得半导体封装上的多个I / O端子（32） （10）暴露。

公开(公告)号：US20080099784A1

公开(公告)日：2008-05-01

申请号：US11554920

申请日：2006-10-31

申请人： Wai Yew Lo ,  Heng Keong Yip

发明人： Wai Yew Lo ,  Heng Keong Yip

IPC分类号： H01L31/00

CPC分类号： H01L21/568 ,  H01L21/561 ,  H01L23/3107 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An array QFN package (10) includes a first semiconductor package (12) and a lead frame (14) having a plurality of leads (16). A first IC die (22) is attached on a first side to the first semiconductor package (12) and is electrically connected to the leads (16) of the lead frame (14). A mold compound (30) encapsulates the first IC die (22), a portion of the first semiconductor package (12) and a portion of the leads (16) such that a plurality of I/O terminals (32) on the semiconductor package (10) is exposed.

摘要翻译： 阵列QFN封装（10）包括具有多个引线（16）的第一半导体封装（12）和引线框架（14）。 第一IC芯片（22）在第一侧附接到第一半导体封装（12）并且电连接到引线框架（14）的引线（16）。 模具化合物（30）封装第一IC管芯（22），第一半导体封装（12）的一部分和引线（16）的一部分，使得半导体封装上的多个I / O端子（32） （10）暴露。

公开(公告)号：US07955953B2

公开(公告)日：2011-06-07

申请号：US11957486

申请日：2007-12-17

申请人： Wai Yew Lo ,  Heng Keong Yip

发明人： Wai Yew Lo ,  Heng Keong Yip

IPC分类号： H01L21/00 ,  H01L23/495

CPC分类号： H01L21/6835 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/85001 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/0665 ,  H01L2224/92247 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method of packaging semiconductor integrated circuits, including the steps of providing a transfer film and forming a patterned, conductive layer on a surface of the transfer film. A first semiconductor integrated circuit (IC) then is attached to the transfer film, where an active side of the first IC is attached to the transfer film. A second semiconductor IC then is attached to the first IC, where a bottom side of the second IC is attached to a bottom side of the first IC. Die pads on an active surface of the second IC are electrically connected to the conductive layer with wires and then a resin material is provided on one side of the transfer film to encapsulate the first and second ICs, the wires and a portion of the conductive layer. Next the transfer film is removed, which exposes the active side of the first IC and the conductive layer. An electrical distribution layer is formed over the active side of the first IC and the conductive layer and conductive balls are attached to the electrical distribution layer. The conductive balls allow electrical interconnection to the first and second integrated circuits.

摘要翻译： 一种封装半导体集成电路的方法，包括以下步骤：在转印膜的表面上提供转印膜并形成图案化的导电层。 然后，第一半导体集成电路（IC）附接到转印膜，其中第一IC的有源侧附着到转印膜上。 然后，第二半导体IC被附接到第一IC，其中第二IC的底侧附接到第一IC的底侧。 第二IC的有源表面上的焊盘与导体层电连接，然后在转移膜的一侧上设置树脂材料，以封装第一和第二IC，导线和一部分导电层 。 接下来，去除转印膜，其暴露第一IC和导电层的活性侧。 在第一IC的有源侧上形成配电层，导电层和导电球附着在配电层上。 导电球允许与第一和第二集成电路的电互连。

公开(公告)号：US20070281393A1

公开(公告)日：2007-12-06

申请号：US11421006

申请日：2006-05-30

申请人： Viswanadam Gautham ,  Lan Chu Tan ,  Heng Keong Yip

发明人： Viswanadam Gautham ,  Lan Chu Tan ,  Heng Keong Yip

IPC分类号： H01L21/60

CPC分类号： H01L21/561 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/81 ,  H01L24/85 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method of forming a semiconductor package (32) includes etching a conductive sheet (10) to form a first interconnection system (12). An integrated circuit (IC) die (22) is placed on and electrically connected to the first interconnection system (12). Next, a molding operation is performed to encapsulate the IC die (22), the electrical connections (24, 26) and at least a portion of the first interconnection system (12). A portion (20) of the conductive sheet (10) is then removed to expose a surface (30) of the first interconnection system (12). A second interconnection system (34) then is formed over the exposed surface (30) of the first interconnection system (12).

摘要翻译： 形成半导体封装（32）的方法包括蚀刻导电片（10）以形成第一互连系统（12）。 集成电路（IC）管芯（22）放置在电连接到第一互连系统（12）上。 接下来，执行模制操作以封装IC管芯（22），电连接（24,26）和第一互连系统（12）的至少一部分。 然后去除导电片（10）的一部分（20）以暴露第一互连系统（12）的表面（30）。 然后在第一互连系统（12）的暴露表面（30）上形成第二互连系统（34）。

公开(公告)号：US07494924B2

公开(公告)日：2009-02-24

申请号：US11370387

申请日：2006-03-06

申请人： Hei Ming Shiu ,  On Lok Chau ,  Gor Amie Lai ,  Heng Keong Yip ,  Thoon Khin Chang ,  Lan Chu Tan

发明人： Hei Ming Shiu ,  On Lok Chau ,  Gor Amie Lai ,  Heng Keong Yip ,  Thoon Khin Chang ,  Lan Chu Tan

IPC分类号： H01L21/44

CPC分类号： H05K3/4015 ,  H01L21/4853 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/11312 ,  H01L2224/1134 ,  H01L2224/118 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/13144 ,  H01L2224/13194 ,  H01L2224/81011 ,  H01L2224/81193 ,  H01L2924/00011 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/351 ,  H05K3/3457 ,  H05K2201/0367 ,  H05K2203/049 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/81805

摘要： A method for forming reinforced interconnects or bumps on a substrate includes first forming a support structure on the substrate. A substantially filled capsule is then formed around the support structure to form an interconnect. The interconnect can reach a height of up to 300 microns.

摘要翻译： 用于在衬底上形成增强互连或凸起的方法包括首先在衬底上形成支撑结构。 然后在支撑结构周围形成基本上填充的胶囊，以形成互连。 互连可以达到高达300微米的高度。

公开(公告)号：US07384819B2

公开(公告)日：2008-06-10

申请号：US11414440

申请日：2006-04-28

申请人： Heng Keong Yip ,  Lan Chu Tan

发明人： Heng Keong Yip ,  Lan Chu Tan

IPC分类号： H01L21/44

CPC分类号： H01L23/49531 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/105 ,  H01L2224/16 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/4911 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A method of forming a semiconductor package (50 and 52) includes providing a substrate (14) having a die pad and bond pads on a first surface (20) and conductive pads (66, 68 and 74) on a second surface (22). An integrated circuit (IC) die (38) is attached to the die pad and the first surface (20) of the substrate (14) is attached to a lead frame (26). The substrate (14) is electrically connected to the lead frame (26), and the IC die (38) is electrically connected to the substrate (14) and the lead frame (26). The IC die (14), the electrical connections (40, 42 and 44), a portion of the substrate (14) and a portion of the lead frame (26) are encapsulated with a mold compound (46), forming a stackable package (48). The conductive pads (66, 68 and 74) on the second surface (22) of the substrate (14) are not encapsulated by the mold compound (46).

摘要翻译： 形成半导体封装（50和52）的方法包括提供在第二表面（22）上的第一表面（20）和导电焊盘（66,68和74）上具有管芯焊盘和焊盘的衬底（14） 。 集成电路（IC）管芯（38）附接到管芯焊盘，衬底（14）的第一表面（20）附接到引线框架（26）。 基板（14）电连接到引线框架（26），并且IC管芯（38）电连接到基板（14）和引线框架（26）。 IC模头（14），电连接（40,42和44），衬底（14）的一部分和引线框架（26）的一部分用模具化合物（46）封装，形成可堆叠封装 （48）。 衬底（14）的第二表面（22）上的导电焊盘（66,68和74）不被模制化合物（46）封装。