Method of forming stackable package

Invention Grant

US07384819B2 Method of forming stackable package 有权

Title translation: 形成可堆叠包装的方法

Please log in to see more content

Patent Title: Method of forming stackable package
Patent Title (中): 形成可堆叠包装的方法
Application No.: US11414440

Application Date: 2006-04-28
Publication No.: US07384819B2

Publication Date: 2008-06-10
Inventor: Heng Keong Yip , Lan Chu Tan
Applicant: Heng Keong Yip , Lan Chu Tan
Applicant Address: US TX Austin
Assignee: Freescale Semiconductor, Inc.
Current Assignee: Freescale Semiconductor, Inc.
Current Assignee Address: US TX Austin
Agent Charles Bergere
Main IPC: H01L21/44
IPC: H01L21/44

Abstract:

A method of forming a semiconductor package (50 and 52) includes providing a substrate (14) having a die pad and bond pads on a first surface (20) and conductive pads (66, 68 and 74) on a second surface (22). An integrated circuit (IC) die (38) is attached to the die pad and the first surface (20) of the substrate (14) is attached to a lead frame (26). The substrate (14) is electrically connected to the lead frame (26), and the IC die (38) is electrically connected to the substrate (14) and the lead frame (26). The IC die (14), the electrical connections (40, 42 and 44), a portion of the substrate (14) and a portion of the lead frame (26) are encapsulated with a mold compound (46), forming a stackable package (48). The conductive pads (66, 68 and 74) on the second surface (22) of the substrate (14) are not encapsulated by the mold compound (46).

Abstract(Chinese):

形成半导体封装（50和52）的方法包括提供在第二表面（22）上的第一表面（20）和导电焊盘（66,68和74）上具有管芯焊盘和焊盘的衬底（14）。集成电路（IC）管芯（38）附接到管芯焊盘，衬底（14）的第一表面（20）附接到引线框架（26）。基板（14）电连接到引线框架（26），并且IC管芯（38）电连接到基板（14）和引线框架（26）。 IC模头（14），电连接（40,42和44），衬底（14）的一部分和引线框架（26）的一部分用模具化合物（46）封装，形成可堆叠封装（48）。衬底（14）的第二表面（22）上的导电焊盘（66,68和74）不被模制化合物（46）封装。

Public/Granted literature

US20070254409A1 Method of forming stackable package Public/Granted day:2007-11-01

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/02	.半导体器件或其部件的制造或处理
H01L21/04	..至少具有一个跃变势垒或表面势垒的器件，例如PN结、耗尽层、载体集结层
H01L21/34	...具有H01L21/06，H01L21/16及H01L21/18各组不包含的或有或无杂质，例如掺杂材料的半导体的器件
H01L21/44	....用H01L21/36至H01L21/428各组不包含的方法或设备在半导体材料上制造电极的