公开(公告)号：US20160172493A1

公开(公告)日：2016-06-16

申请号：US15051734

申请日：2016-02-24

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Shao Ming Koh ,  Guillaume Bouche ,  Jeremy A. Wahl ,  Andy C. Wei

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/161 ,  H01L27/092 ,  H01L29/08 ,  H01L29/24 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/7839 ,  H01L21/02532 ,  H01L21/31111 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/167 ,  H01L29/24 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665 ,  H01L29/7848

Abstract: Integrated circuits having silicide contacts with reduced contact resistance and methods for fabricating integrated circuits having silicide contacts with reduced contact resistance are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with fin structures having source/drain regions in PFET areas and in NFET areas. The method includes selectively forming a contact resistance modulation material on the source/drain regions in the PFET areas. Further, the method includes depositing a band-edge workfunction metal overlying the source/drain regions in the PFET areas and in the NFET areas.

Abstract translation: 提供了具有降低的接触电阻的硅化物接触的集成电路和用于制造具有降低的接触电阻的具有硅化物接触的集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括：在PFET区域和NFET区域中提供具有鳍状结构的鳍状结构的源极/漏极区域。 该方法包括在PFET区域中的源/漏区上选择性地形成接触电阻调制材料。 此外，该方法包括沉积覆盖PFET区域和NFET区域中的源极/漏极区域的带边功函数金属。

公开(公告)号：US09634143B1

公开(公告)日：2017-04-25

申请号：US15215921

申请日：2016-07-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jeremy A. Wahl ,  Ryan W. Sporer

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L21/84 ,  H01L29/417

CPC classification number: H01L29/7848 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/823892 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/0928 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791

Abstract: One disclosed method includes forming a fin in a substrate by etching a plurality of fin-formation trenches, forming a layer of insulating material in the trenches, performing a densification anneal process on the layer of insulating material and, after performing the densification anneal process, performing at least one ion implantation process to form a counter-doped well region in the fin. The method also includes forming an undoped semiconductor material on an exposed upper surface of the fin, recessing the insulating material so as to expose at least a portion of the undoped semiconductor material and forming a gate structure around the exposed portion of the undoped semiconductor material.

公开(公告)号：US09293462B2

公开(公告)日：2016-03-22

申请号：US14167778

申请日：2014-01-29

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Shao Ming Koh ,  Guillaume Bouche ,  Jeremy A. Wahl ,  Andy C. Wei

IPC: H01L21/4763 ,  H01L27/092 ,  H01L21/311 ,  H01L29/45 ,  H01L21/8238 ,  H01L29/16 ,  H01L29/167 ,  H01L29/161

CPC classification number: H01L29/7839 ,  H01L21/02532 ,  H01L21/31111 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/167 ,  H01L29/24 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665 ,  H01L29/7848

Abstract: Integrated circuits having silicide contacts with reduced contact resistance and methods for fabricating integrated circuits having silicide contacts with reduced contact resistance are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having selected source/drain regions and non-selected source/drain regions. The method forms a contact resistance modulation material over the selected source/drain regions. Further, the method forms a metal layer over the selected and non-selected source/drain regions. The method includes annealing the metal layer to form silicide contacts on the selected and non-selected source/drain regions.

Abstract translation: 提供了具有降低的接触电阻的硅化物接触的集成电路和用于制造具有降低的接触电阻的具有硅化物接触的集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括提供具有所选择的源极/漏极区域和未选择的源极/漏极区域的半导体衬底。 该方法在选定的源极/漏极区域上形成接触电阻调制材料。 此外，该方法在所选择的和非选择的源/漏区上形成金属层。 该方法包括退火金属层以在所选择的和非选择的源/漏区上形成硅化物接触。

公开(公告)号：US08691640B1

公开(公告)日：2014-04-08

申请号：US13745927

申请日：2013-01-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nicholas V. LiCausi ,  Jeremy A. Wahl

IPC: H01L21/00

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: One illustrative method disclosed herein includes forming a plurality of trenches in a semiconductor substrate to thereby define an initial fin structure, forming sidewall spacers adjacent the initial fin structure, wherein the spacers cover a first portion of the initial fin structure and expose a second a portion of the initial fin structure, performing a doping process to form N-type doped regions in at least the exposed portion of the initial fin structure, and performing an etching process to remove at least a portion of the doped regions and thereby define a final fin structure that is vertically spaced apart from the substrate.

Abstract translation: 本文公开的一种示例性方法包括在半导体衬底中形成多个沟槽，从而限定初始鳍结构，形成邻近初始鳍结构的侧壁间隔物，其中间隔物覆盖初始鳍结构的第一部分并暴露第二部分 的初始鳍结构，执行掺杂工艺以在至少初始鳍结构的暴露部分中形成N型掺杂区，并且执行蚀刻工艺以去除至少一部分掺杂区域，从而限定最终鳍 与衬底垂直间隔开的结构。

公开(公告)号：US10707119B1

公开(公告)日：2020-07-07

申请号：US16246847

申请日：2019-01-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nicholas V. LiCausi ,  Jeremy A. Wahl ,  Vimal K. Kamineni

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: Structures that include interconnects and methods for forming a structure that includes interconnects. A metallization level includes a metallization level having a first interconnect with a first top surface, a second interconnect with a second top surface, and a cavity with an entrance between the first interconnect and the second interconnect. A first dielectric layer includes a first section arranged on the first top surface of the first interconnect and a second section arranged on the second top surface of the second interconnect. The first section of the first dielectric layer is separated from the second section of the first dielectric layer by the entrance of the cavity. A second dielectric layer is arranged to surround the cavity and to close the entrance to the cavity in order to encapsulate an airgap inside the cavity.

公开(公告)号：US09196694B2

公开(公告)日：2015-11-24

申请号：US14043017

申请日：2013-10-01

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Guillaume Bouche ,  Shao Ming Koh ,  Jeremy A. Wahl ,  Andy Wei

IPC: H01L21/44 ,  H01L29/417 ,  H01L27/092

CPC classification number: H01L29/45 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/41725

Abstract: Integrated circuits with dual silicide contacts and methods for fabricating integrated circuits with dual silicide contacts are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having PFET areas and NFET areas. The method selectively forms first silicide contacts from a first metal in the PFET areas. Further, the method selectively forms second silicide contacts from a second metal in the NFET areas. The second metal is different from the first metal.

Abstract translation: 提供了具有双硅化物触点的集成电路和用于制造具有双硅化物触点的集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括提供具有PFET区域和NFET区域的半导体衬底。 该方法选择性地从PFET区域中的第一金属形成第一硅化物接触。 此外，该方法从NFET区域中的第二金属选择性地形成第二硅化物接触。 第二种金属与第一种金属不同。

公开(公告)号：US09177805B2

公开(公告)日：2015-11-03

申请号：US14166660

申请日：2014-01-28

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Guillaume Bouche ,  Shao Ming Koh ,  Jeremy A. Wahl ,  Andy C. Wei

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/2807 ,  H01L21/28158 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795

Abstract: Integrated circuits having metal-insulator-semiconductor (MIS) contact structures and methods for fabricating integrated circuits having metal-insulator-semiconductor (MIS) contact structures are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a fin structure formed from semiconductor material overlying a semiconductor substrate. The method includes depositing a layer of high-k dielectric material over the fin structure. Further, the method includes forming a metal layer or layers over the layer of high-k dielectric material to provide the fin structure with a metal-insulator-semiconductor (MIS) contact structure.

Abstract translation: 提供了具有金属 - 绝缘体半导体（MIS）接触结构的集成电路以及用于制造具有金属 - 绝缘体 - 半导体（MIS））接触结构的集成电路的方法。 在一个实施例中，制造集成电路的方法包括提供由半导体材料覆盖在半导体衬底上形成的鳍结构。 该方法包括在鳍结构上沉积高k电介质材料层。 此外，该方法包括在高k电介质材料层上形成金属层，以使鳍结构具有金属 - 绝缘体半导体（MIS）接触结构。

公开(公告)号：US20150214228A1

公开(公告)日：2015-07-30

申请号：US14167778

申请日：2014-01-29

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Shao Ming Koh ,  Guillaume Bouche ,  Jeremy A. Wahl ,  Andy C. Wei

IPC: H01L27/092 ,  H01L29/45 ,  H01L29/161 ,  H01L21/02 ,  H01L29/16 ,  H01L29/167 ,  H01L21/311 ,  H01L21/8238

CPC classification number: H01L29/7839 ,  H01L21/02532 ,  H01L21/31111 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/167 ,  H01L29/24 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665 ,  H01L29/7848

Abstract: Integrated circuits having silicide contacts with reduced contact resistance and methods for fabricating integrated circuits having silicide contacts with reduced contact resistance are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having selected source/drain regions and non-selected source/drain regions. The method forms a contact resistance modulation material over the selected source/drain regions. Further, the method forms a metal layer over the selected and non-selected source/drain regions. The method includes annealing the metal layer to form silicide contacts on the selected and non-selected source/drain regions.

Abstract translation: 提供了具有降低的接触电阻的硅化物接触的集成电路和用于制造具有降低的接触电阻的具有硅化物接触的集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括提供具有选定的源极/漏极区域和未选择的源极/漏极区域的半导体衬底。 该方法在选定的源极/漏极区域上形成接触电阻调制材料。 此外，该方法在所选择的和非选择的源/漏区上形成金属层。 该方法包括退火金属层以在所选择的和非选择的源/漏区上形成硅化物接触。

公开(公告)号：US08963255B2

公开(公告)日：2015-02-24

申请号：US14219910

申请日：2014-03-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jeremy A. Wahl ,  Kingsuk Maitra

IPC: H01L29/76 ,  H01L29/94

CPC classification number: H01L27/092 ,  H01L21/26506 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/66651 ,  H01L29/78

Abstract: A semiconductor is formed on a (110) silicon (Si) substrate, with improved electron mobility. Embodiments include semiconductor devices having a silicon carbide (SiC) portion in the nFET channel region. An embodiment includes forming an nFET channel region and a pFET channel region in a Si substrate, such as a (110) Si substrate, and forming a silicon carbide (SiC) portion on the nFET channel region. The SiC portion may be formed by ion implantation of C followed by a recrystallization anneal or by epitaxial growth of SiC in a recess formed in the substrate. The use of SiC in the nFET channel region improves electron mobility without introducing topographical differences between NMOS and PMOS transistors.

Abstract translation: 在（110）硅（Si）衬底上形成半导体，具有改善的电子迁移率。 实施例包括在nFET沟道区域中具有碳化硅（SiC）部分的半导体器件。 一个实施例包括在诸如（110）Si衬底的Si衬底中形成nFET沟道区和pFET沟道区，并在nFET沟道区上形成碳化硅（SiC）部分。 SiC部分可以通过C的离子注入，然后通过在衬底中形成的凹陷中的SiC再结晶退火或外延生长来形成。 在nFET通道区域中使用SiC可以提高电子迁移率，而不会导致NMOS和PMOS晶体管之间的形貌差异。

公开(公告)号：US08846511B2

公开(公告)日：2014-09-30

申请号：US13764839

申请日：2013-02-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nicholas V. LiCausi ,  Jeremy A. Wahl

IPC: H01L21/00 ,  H01L29/66

CPC classification number: H01L29/66477 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/775

Abstract: One illustrative method disclosed herein includes forming an initial nanowire structure having an initial cross-sectional size, performing a doping diffusion process to form an N-type doped region in the initial nanowire structure and performing an etching process to remove at least a portion of the doped region and thereby define a final nanowire structure having a final cross-sectional size, wherein the final cross-sectional size is smaller than the initial cross-sectional size.

Abstract translation: 本文公开的一种说明性方法包括形成具有初始横截面尺寸的初始纳米线结构，执行掺杂扩散工艺以在初始纳米线结构中形成N型掺杂区，并执行蚀刻工艺以去除至少一部分 从而限定具有最终横截面尺寸的最终纳米线结构，其中最终横截面尺寸小于初始横截面尺寸。