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公开(公告)号：US20190013268A1
公开(公告)日：2019-01-10
申请号：US16127645
申请日：2018-09-11
发明人： Andrew M. Greene , Injo Ok , Balasubramanian Pranatharthiharan , Charan V.V.S. Surisetty , Ruilong Xie
IPC分类号： H01L23/528 , H01L21/768 , H01L29/49 , H01L21/283 , H01L21/3205 , H01L29/66 , H01L21/3213 , H01L21/306 , H01L27/088 , H01L29/417 , H01L21/8234 , H01L29/78
摘要： A self-aligned interconnect structure includes a fin structure patterned in a substrate; an epitaxial contact disposed over the fin structure; a first metal gate and a second metal gate disposed over and substantially perpendicular to the epitaxial contact, the first metal gate and the second metal gate being substantially parallel to one another; and a metal contact on and in contact with the substrate in a region between the first and second metal gates.
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公开(公告)号：US09698101B2
公开(公告)日：2017-07-04
申请号：US14839108
申请日：2015-08-28
发明人： Andrew M. Greene , Injo Ok , Balasubramanian Pranatharthiharan , Charan V. V. S. Surisetty , Ruilong Xie
IPC分类号： H01L27/088 , H01L23/528 , H01L29/78 , H01L29/66 , H01L21/768 , H01L21/306 , H01L21/3205 , H01L21/283 , H01L21/3213 , H01L29/49
CPC分类号： H01L23/528 , H01L21/283 , H01L21/30604 , H01L21/3205 , H01L21/32133 , H01L21/76829 , H01L21/76831 , H01L21/76877 , H01L21/76895 , H01L21/76897 , H01L21/823431 , H01L27/0886 , H01L29/41791 , H01L29/4916 , H01L29/66545 , H01L29/6681 , H01L29/785
摘要： A self-aligned interconnect structure includes a fin structure patterned in a substrate; an epitaxial contact disposed over the fin structure; a first metal gate and a second metal gate disposed over and substantially perpendicular to the epitaxial contact, the first metal gate and the second metal gate being substantially parallel to one another; and a metal contact on and in contact with the substrate in a region between the first and second metal gates.
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公开(公告)号：US20170104100A1
公开(公告)日：2017-04-13
申请号：US14879220
申请日：2015-10-09
申请人： GLOBALFOUNDRIES Inc.
发明人： Emre Alptekin , Lars W. Liebmann , Injo Ok , Balasubramanian Pranatharthiharan , Ravikumar Ramachandran , Soon-Cheon Seo , Charan V.V.S. Surisetty , Mickey H. Yu
IPC分类号： H01L29/78 , H01L21/8234 , H01L27/088
CPC分类号： H01L29/7848 , H01L21/32139 , H01L21/823418 , H01L21/823425 , H01L21/823431 , H01L21/823437 , H01L21/823475 , H01L27/0886 , H01L29/401 , H01L29/66636 , H01L29/66795
摘要： Various embodiments include methods and integrated circuit structures. In some cases, a method of forming an integrated circuit structure can include: forming a doped silicon layer over a substrate; forming a plurality of fin structures from the doped silicon layer; forming a plurality of gate structures over the plurality of fin structures, each of the plurality of gate structures separated from a neighboring gate structure by a first pitch; forming a mask over the plurality of gate structures, exposing at least one of the plurality of gate structures; removing the at least one of the plurality of gate structures, wherein two of the remaining gate structures after the removing are separated by a second pitch larger than the first pitch; and forming an epitaxial region over the substrate between the two of the remaining gate structures.
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4.发明申请METHODS FOR PRODUCING INTEGRATED CIRCUITS USING LONG AND SHORT REGIONS AND INTEGRATED CIRCUITS PRODUCED FROM SUCH METHODS 有权使用长期和短期地区生产集成电路的方法以及从这些方法生产的集成电路公开(公告)号：US20170012107A1
公开(公告)日：2017-01-12
申请号：US14795984
申请日：2015-07-10
发明人： Chanro Park , Injo Ok
CPC分类号： H01L29/4966 , H01L21/28088 , H01L21/70 , H01L21/82 , H01L21/82345 , H01L21/823456 , H01L29/66545
摘要： Integrated circuits and methods for producing the same are provided. In an exemplary embodiment, a method for producing an integrated circuit includes forming a work function layer overlying a substrate and a plurality of dielectric columns. The dielectric columns and the substrate define a short region having a short region width and a long region having a long region width greater than the short region width. The work function layer is recessed in the long region to a long region work function height that is between a dielectric column top surface and a substrate top surface. The work function layer is also recessed in the short region to a short region work function height that is between the dielectric column top surface and the substrate top surface. Recessing the work function layer in the long and short regions is conducted in the absence of lithography techniques.
摘要翻译： 提供了集成电路及其制造方法。 在示例性实施例中，用于制造集成电路的方法包括形成覆盖在基板和多个电介质柱上的功函数层。 电介质柱和衬底限定具有短区域宽度的短区域和具有大于短区域宽度的长区域宽度的长区域。 工作功能层在长区域中凹陷到介电柱顶表面和基板顶表面之间的长区域功函数高度。 工作功能层也在短区域中凹陷到介电柱顶表面和衬底顶表面之间的短区域功函数高度。 在没有光刻技术的情况下，在长和短区域内嵌入功函数层。
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5.发明授权Methods for producing integrated circuits using long and short regions and integrated circuits produced from such methods 有权使用长和短区域制造集成电路的方法和由这些方法制造的集成电路公开(公告)号：US09583584B2
公开(公告)日：2017-02-28
申请号：US14795984
申请日：2015-07-10
发明人： Chanro Park , Injo Ok
CPC分类号： H01L29/4966 , H01L21/28088 , H01L21/70 , H01L21/82 , H01L21/82345 , H01L21/823456 , H01L29/66545
摘要： Integrated circuits and methods for producing the same are provided. In an exemplary embodiment, a method for producing an integrated circuit includes forming a work function layer overlying a substrate and a plurality of dielectric columns. The dielectric columns and the substrate define a short region having a short region width and a long region having a long region width greater than the short region width. The work function layer is recessed in the long region to a long region work function height that is between a dielectric column top surface and a substrate top surface. The work function layer is also recessed in the short region to a short region work function height that is between the dielectric column top surface and the substrate top surface. Recessing the work function layer in the long and short regions is conducted in the absence of lithography techniques.
摘要翻译： 提供了集成电路及其制造方法。 在示例性实施例中，用于制造集成电路的方法包括形成覆盖在基板和多个电介质柱上的功函数层。 电介质柱和衬底限定具有短区域宽度的短区域和具有大于短区域宽度的长区域宽度的长区域。 工作功能层在长区域中凹陷到介电柱顶表面和基板顶表面之间的长区域功函数高度。 工作功能层也在短区域中凹陷到介电柱顶表面和衬底顶表面之间的短区域功函数高度。 在没有光刻技术的情况下，在长和短区域内嵌入功函数层。
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公开(公告)号：US20170062325A1
公开(公告)日：2017-03-02
申请号：US14839108
申请日：2015-08-28
发明人： Andrew M. Greene , Injo Ok , Balasubramanian Pranatharthiharan , Charan V.V.S. Surisetty , Ruilong Xie
IPC分类号： H01L23/528 , H01L29/66 , H01L21/768 , H01L29/49 , H01L21/3205 , H01L21/283 , H01L21/3213 , H01L29/78 , H01L21/306
CPC分类号： H01L23/528 , H01L21/283 , H01L21/30604 , H01L21/3205 , H01L21/32133 , H01L21/76829 , H01L21/76831 , H01L21/76877 , H01L21/76895 , H01L21/76897 , H01L21/823431 , H01L27/0886 , H01L29/41791 , H01L29/4916 , H01L29/66545 , H01L29/6681 , H01L29/785
摘要： A self-aligned interconnect structure includes a fin structure patterned in a substrate; an epitaxial contact disposed over the fin structure; a first metal gate and a second metal gate disposed over and substantially perpendicular to the epitaxial contact, the first metal gate and the second metal gate being substantially parallel to one another; and a metal contact on and in contact with the substrate in a region between the first and second metal gates.
摘要翻译： 自对准互连结构包括在衬底中图案化的翅片结构; 设置在所述鳍结构上的外延触点; 第一金属栅极和第二金属栅极，其设置在外延接触面上并基本上垂直于外延接触，第一金属栅极和第二金属栅极基本上彼此平行; 以及在第一和第二金属栅极之间的区域中与基板接触并与之接触的金属接触。
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公开(公告)号：US10325848B2
公开(公告)日：2019-06-18
申请号：US16127645
申请日：2018-09-11
发明人： Andrew M. Greene , Injo Ok , Balasubramanian Pranatharthiharan , Charan V. V. S. Surisetty , Ruilong Xie
IPC分类号： H01L29/49 , H01L23/528 , H01L29/78 , H01L29/66 , H01L21/768 , H01L21/306 , H01L21/3205 , H01L21/283 , H01L21/3213 , H01L21/8234 , H01L29/417 , H01L27/088
摘要： A self-aligned interconnect structure includes a fin structure patterned in a substrate; an epitaxial contact disposed over the fin structure; a first metal gate and a second metal gate disposed over and substantially perpendicular to the epitaxial contact, the first metal gate and the second metal gate being substantially parallel to one another; and a metal contact on and in contact with the substrate in a region between the first and second metal gates.
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公开(公告)号：US10236253B2
公开(公告)日：2019-03-19
申请号：US15484309
申请日：2017-04-11
发明人： Andrew M. Greene , Injo Ok , Balasubramanian Pranatharthiharan , Charan V. V. S. Surisetty , Ruilong Xie
IPC分类号： H01L27/088 , H01L23/528 , H01L29/78 , H01L29/66 , H01L21/768 , H01L21/306 , H01L21/3205 , H01L21/283 , H01L21/3213 , H01L29/49 , H01L21/8234 , H01L29/417
摘要： A self-aligned interconnect structure includes a fin structure patterned in a substrate; an epitaxial contact disposed over the fin structure; a first metal gate and a second metal gate disposed over and substantially perpendicular to the epitaxial contact, the first metal gate and the second metal gate being substantially parallel to one another; and a metal contact on and in contact with the substrate in a region between the first and second metal gates.
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公开(公告)号：US09818873B2
公开(公告)日：2017-11-14
申请号：US14879220
申请日：2015-10-09
申请人： GLOBALFOUNDRIES Inc.
发明人： Emre Alptekin , Lars W. Liebmann , Injo Ok , Balasubramanian Pranatharthiharan , Ravikumar Ramachandran , Soon-Cheon Seo , Charan V. V. S. Surisetty , Mickey H. Yu
IPC分类号： H01L29/40 , H01L29/78 , H01L27/088 , H01L21/8234 , H01L29/66 , H01L21/3213
CPC分类号： H01L29/7848 , H01L21/32139 , H01L21/823418 , H01L21/823425 , H01L21/823431 , H01L21/823437 , H01L21/823475 , H01L27/0886 , H01L29/401 , H01L29/66636 , H01L29/66795
摘要： Various embodiments include methods and integrated circuit structures. In some cases, a method of forming an integrated circuit structure can include: forming a doped silicon layer over a substrate; forming a plurality of fin structures from the doped silicon layer; forming a plurality of gate structures over the plurality of fin structures, each of the plurality of gate structures separated from a neighboring gate structure by a first pitch; forming a mask over the plurality of gate structures, exposing at least one of the plurality of gate structures; removing the at least one of the plurality of gate structures, wherein two of the remaining gate structures after the removing are separated by a second pitch larger than the first pitch; and forming an epitaxial region over the substrate between the two of the remaining gate structures.
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公开(公告)号：US20170221808A1
公开(公告)日：2017-08-03
申请号：US15484309
申请日：2017-04-11
发明人： Andrew M. Greene , Injo Ok , Balasubramanian Pranatharthiharan , Charan V.V.S. Surisetty , Ruilong Xie
IPC分类号： H01L23/528 , H01L21/306 , H01L29/66 , H01L21/768 , H01L29/49 , H01L29/78
CPC分类号： H01L23/528 , H01L21/283 , H01L21/30604 , H01L21/3205 , H01L21/32133 , H01L21/76829 , H01L21/76831 , H01L21/76877 , H01L21/76895 , H01L21/76897 , H01L21/823431 , H01L27/0886 , H01L29/41791 , H01L29/4916 , H01L29/66545 , H01L29/6681 , H01L29/785
摘要： A self-aligned interconnect structure includes a fin structure patterned in a substrate; an epitaxial contact disposed over the fin structure; a first metal gate and a second metal gate disposed over and substantially perpendicular to the epitaxial contact, the first metal gate and the second metal gate being substantially parallel to one another; and a metal contact on and in contact with the substrate in a region between the first and second metal gates.
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