公开(公告)号：US20050189629A1

公开(公告)日：2005-09-01

申请号：US11066174

申请日：2005-02-28

Applicant: Fujio Ito ,  Hiromichi Suzuki ,  Tokuji Toida

Inventor： Fujio Ito ,  Hiromichi Suzuki ,  Tokuji Toida

IPC: B65D77/30 ,  B65D81/26 ,  B65D85/86 ,  B65D85/90 ,  H01L21/00 ,  H01L21/48 ,  H01L21/673 ,  H01L23/00 ,  H01L23/495

CPC classification number: H01L23/49503 ,  H01L21/6735 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01021 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method for manufacturing a semiconductor device includes the steps of providing a semiconductor device of a surface mounted type in which the main surface of a chip mounting portion connected to a semiconductor chip is formed so as to be smaller than the main surface of the semiconductor chip, accommodating the semiconductor device into a non-moistureproof, e.g., flammable, packing, and shipping the packed semiconductor device. The non-moistureproof packing may have a moisture permeability of T T≧1 g/m2/24 hr. The method may also include providing a second semiconductor device of a surface-mounted type in which the main surface of a chip mounting portion connected to a semiconductor chip is formed so as to be larger than the main surface of the semiconductor chip, moistureproof-packing the second semiconductor device, and shipping and packed second semiconductor device.

Abstract translation: 一种制造半导体器件的方法包括以下步骤：提供一种表面安装型半导体器件，其中连接到半导体芯片的芯片安装部分的主表面形成为小于半导体芯片的主表面 ，将半导体器件容纳在非防潮的（例如，易燃，包装）中，并运输封装的半导体器件。 非防潮包装可具有T T> = 1g / m 2 / 24hr的透湿性。 该方法还可以包括提供表面安装型的第二半导体器件，其中连接到半导体芯片的芯片安装部分的主表面形成为大于半导体芯片的主表面，防潮包装 第二半导体器件，以及运输和封装的第二半导体器件。

公开(公告)号：US06396142B1

公开(公告)日：2002-05-28

申请号：US09369402

申请日：1999-08-06

Applicant: Fujio Ito ,  Hiroaki Tanaka ,  Hiromichi Suzuki ,  Tokuji Toida ,  Takafumi Konno ,  Kunihiro Tsubosaki ,  Shigeki Tanaka ,  Kazunari Suzuki ,  Akihiko Kameoka

Inventor： Fujio Ito ,  Hiroaki Tanaka ,  Hiromichi Suzuki ,  Tokuji Toida ,  Takafumi Konno ,  Kunihiro Tsubosaki ,  Shigeki Tanaka ,  Kazunari Suzuki ,  Akihiko Kameoka

IPC: H01L2348

CPC classification number: H01L24/32 ,  H01L23/4334 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/29007 ,  H01L2224/32014 ,  H01L2224/32055 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/49171 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/85385 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/01026 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: In a semiconductor device having a heat radiation plate, the tips of inner leads connected to a semiconductor chip have a lead width w and a lead thickness t, the width being less than the thickness. The inner leads are secured to the heat radiation plate. Fastening the inner leads to the heat radiation plate supports the latter and eliminates the need for suspending leads. A lead pitch p, the lead width w and lead thickness t of the inner lead tips connected to the semiconductor chip have the relations of w

公开(公告)号：US06803258B2

公开(公告)日：2004-10-12

申请号：US10152727

申请日：2002-05-23

Applicant: Fujio Ito ,  Hiroaki Tanaka ,  Hiromichi Suzuki ,  Tokuji Toida ,  Takafumi Konno ,  Kunihiro Tsubosaki ,  Shigeki Tanaka ,  Kazunari Suzuki ,  Akihiko Kameoka

Inventor： Fujio Ito ,  Hiroaki Tanaka ,  Hiromichi Suzuki ,  Tokuji Toida ,  Takafumi Konno ,  Kunihiro Tsubosaki ,  Shigeki Tanaka ,  Kazunari Suzuki ,  Akihiko Kameoka

IPC: H01L2150

CPC classification number: H01L24/32 ,  H01L23/4334 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/29007 ,  H01L2224/32014 ,  H01L2224/32055 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/49171 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/85385 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/01026 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: In a semiconductor device having a heat radiation plate, the tips of inner leads connected to a semiconductor chip have a lead width w and a lead thickness t, the width being less than the thickness. The inner leads are secured to the heat radiation plate. Fastening the inner leads to the heat radiation plate supports the latter and eliminates the need for suspending leads. A lead pitch p, the lead width w and lead thickness t of the inner lead tips connected to the semiconductor chip have the relations of w

Abstract translation: 在具有散热板的半导体器件中，连接到半导体芯片的内部引线的尖端具有引线宽度w和引线厚度t，宽度小于厚度。 内引线固定在散热板上。 将内部引线固定到散热板上，支撑后者，并且不需要悬挂引线。 引线间距p，连接到半导体芯片的内引线头的引线宽度w和引线厚度t具有w

公开(公告)号：US06673655B2

公开(公告)日：2004-01-06

申请号：US10152726

申请日：2002-05-23

Applicant: Fujio Ito ,  Hiroaki Tanaka ,  Hiromichi Suzuki ,  Tokuji Toida ,  Takafumi Konno ,  Kunihiro Tsubosaki ,  Shigeki Tanaka ,  Kazunari Suzuki ,  Akihiko Kameoka

Inventor： Fujio Ito ,  Hiroaki Tanaka ,  Hiromichi Suzuki ,  Tokuji Toida ,  Takafumi Konno ,  Kunihiro Tsubosaki ,  Shigeki Tanaka ,  Kazunari Suzuki ,  Akihiko Kameoka

IPC: H01L2348

CPC classification number: H01L24/32 ,  H01L23/4334 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/29007 ,  H01L2224/32014 ,  H01L2224/32055 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/49171 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/85385 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/01026 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: In a semiconductor device having a heat radiation plate, the tips of inner leads connected to a semiconductor chip have a lead width w and a lead thickness t, the width being less than the thickness. The inner leads are secured to the heat radiation plate. Fastening the inner leads to the heat radiation plate supports the latter and eliminates the need for suspending leads. A lead pitch p, the lead width w and lead thickness t of the inner lead tips connected to the semiconductor chip have the relations of w

Abstract translation: 在具有散热板的半导体器件中，连接到半导体芯片的内部引线的尖端具有引线宽度w和引线厚度t，宽度小于厚度。 内引线固定在散热板上。 将内部引线固定到散热板上，支撑后者，并且不需要悬挂引线。 引线间距p，连接到半导体芯片的内引线头的引线宽度w和引线厚度t具有w

公开(公告)号：US20050189627A1

公开(公告)日：2005-09-01

申请号：US11065108

申请日：2005-02-25

Applicant: Fujio Ito ,  Hiromichi Suzuki ,  Takashi Miwa ,  Tokuji Toida

Inventor： Fujio Ito ,  Hiromichi Suzuki ,  Takashi Miwa ,  Tokuji Toida

IPC: H01L21/48 ,  H01L21/56 ,  H01L21/60 ,  H01L23/12 ,  H01L23/31 ,  H01L23/495 ,  H01L23/50 ,  H05K1/18 ,  H05K3/34

CPC classification number: H01L23/3107 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/49541 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K3/3426 ,  H05K3/3442 ,  H05K2201/09709 ,  H05K2201/10689 ,  H05K2201/10931 ,  H05K2201/10984 ,  Y02P70/613 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A surface mounting method for mounting semiconductor devices suppresses solder peeling defects which tried to occur during mounting. The method used for mounting semiconductor devices includes a process for preparing the semiconductor devices by obtaining multiple terminals by exposing a section of each of multiple leads protruding from a rear side of the plastic casing, and forming a layer of solder by solidifying a molten solder material; a process for supplying a solder paste material to multiple electrodes on a printed circuit board; and a process for melting the solder paste of the multiple electrodes and connecting each of the multiple terminals with the multiple electrodes.

Abstract translation: 用于安装半导体器件的表面安装方法抑制了在安装期间发生的焊料剥离缺陷。 用于安装半导体器件的方法包括通过从塑料外壳的后侧突出的多个引线的一部分暴露出多个端子来制备半导体器件的工艺，以及通过使熔融焊料材料固化形成一层焊料 ; 用于将焊膏材料供应到印刷电路板上的多个电极的工艺; 以及用于熔化多个电极的焊膏并将多个端子中的每一个与多个电极连接的工艺。

公开(公告)号：US20080311703A1

公开(公告)日：2008-12-18

申请号：US12194001

申请日：2008-08-19

Applicant: Fujio Ito ,  Hiromichi Suzuki ,  Toshio Sasaki

Inventor： Fujio Ito ,  Hiromichi Suzuki ,  Toshio Sasaki

IPC: H01L21/82

CPC classification number: H01L23/49541 ,  H01L21/4842 ,  H01L23/49558 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A plurality of inner leads, a plurality of outer leads formed in one with each of the inner lead, a bar lead of the square ring shape arranged inside a plurality of inner leads, a corner part lead which has been arranged between the inner leads of the end portion of the inner lead groups which adjoin among four inner lead groups corresponding to each side of the bar lead, and was connected with the bar lead, and a tape member joined to the tip part of each inner lead, a bar lead, and a corner part lead are included. Since the corner part lead is formed as an object for reinforcement of a frame body between adjoining inner lead groups, the rigidity of the lead frame can be increased.

Abstract translation: 多个内部引线，多个外部引线，每个外部引线与内部引线中的每一个形成一个，方形环形状的引脚布置在多个内部引线内;角部引线，其设置在内部引线之间 所述内引线组的与所述棒引线的每一侧相对应的四个内引线组中相邻的所述内引线组的端部与所述引线连接，以及与所述内引线的前端接合的带部件， 并包括角落部分铅。 由于角部引线形成为在相邻的内引线组之间加强框架体的对象，所以可以提高引线框架的刚性。

公开(公告)号：US07339259B2

公开(公告)日：2008-03-04

申请号：US11712456

申请日：2007-03-01

Applicant: Fujio Ito ,  Hiromichi Suzuki

Inventor： Fujio Ito ,  Hiromichi Suzuki

IPC: H01L23/495 ,  H01L23/48

CPC classification number: H01L23/4951 ,  H01L21/565 ,  H01L23/16 ,  H01L23/49506 ,  H01L23/49548 ,  H01L24/27 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/16145 ,  H01L2224/274 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929 ,  H01L2924/00012 ,  H01L2224/05599

Abstract: A semiconductor device has an improved mounting reliability and has external terminals formed by exposing portions of leads from a back surface of a resin sealing member. End portions on one side of the leads are fixed to a back surface of a semiconductor chip, and portions of the leads positioned outside the semiconductor chip are connected with electrodes formed on the semiconductor chip through wires.

Abstract translation: 半导体器件具有改进的安装可靠性，并且具有通过从树脂密封构件的后表面暴露引线部分而形成的外部端子。 引线一侧的端部固定在半导体芯片的背面，位于半导体芯片外部的引线部分通过导线与形成在半导体芯片上的电极连接。

公开(公告)号：US07199469B2

公开(公告)日：2007-04-03

申请号：US09964484

申请日：2001-09-28

Applicant: Toru Ishida ,  Tetsuharu Urawa ,  Fujio Ito ,  Tomoo Matsuzawa ,  Kazunari Suzuki ,  Akihiko Kameoka ,  Hiromichi Suzuki ,  Takuji Ide

Inventor： Toru Ishida ,  Tetsuharu Urawa ,  Fujio Ito ,  Tomoo Matsuzawa ,  Kazunari Suzuki ,  Akihiko Kameoka ,  Hiromichi Suzuki ,  Takuji Ide

IPC: H01L23/48 ,  H01L23/495 ,  H01L23/50 ,  H01L25/18 ,  H01L25/065

CPC classification number: H01L24/06 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48599 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/4945 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2225/06555 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/48227 ,  H01L2924/00012

Abstract: The cost of a semiconductor device is to be reduced. An electrical connection between a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip is made through an inner lead portion of a lead disposed at a position around the first semiconductor chip and two bonding wires.

Abstract translation: 降低半导体器件的成本。 通过布置在第一半导体芯片周围的引线的引线的内部引线部分和两个接合线来制造堆叠在第一半导体芯片上的第一半导体芯片和第二半导体芯片之间的电连接。

公开(公告)号：US20060186528A1

公开(公告)日：2006-08-24

申请号：US10516417

申请日：2003-05-16

Applicant: Toshio Sasaki ,  Fujio Ito ,  Hiromichi Suzuki

Inventor： Toshio Sasaki ,  Fujio Ito ,  Hiromichi Suzuki

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L24/06 ,  H01L23/49513 ,  H01L23/49531 ,  H01L23/49541 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/29007 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48253 ,  H01L2224/48257 ,  H01L2224/48599 ,  H01L2224/48639 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49431 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/85439 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10162 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012

Abstract: The present invention can supply power for each circuit section by separating and connecting bus-bar (21d) for each circuit section inside the semiconductor chip (22), and, in addition, can increase the number of pads (22a) for power supply or can use the lead (21a) conventionally used for power supply for signals by further making the best of the characteristics that enable the connection to bus-bar (21d) irrespective of the inner lead (21b) pitch, by making the pitch of the pad (22a) smaller than the pitch of the inner lead (21b), or by forming the pad (22a) in a zigzag arrangement.

Abstract translation: 本发明可以通过对半导体芯片（22）内部的每个电路部分的汇流条（21d）进行分离和连接来为每个电路部分供电，并且还可以增加用于功率的焊盘（22a）的数量 提供或可以使用通常用于信号电源的引线（21a），通过进一步充分利用能够连接到母线（21d）而不考虑内部引线（21b）间距的特性，通过制造 衬垫（22a）的间距小于内引线（21b）的间距，或通过以锯齿形布置形成焊盘（22a）。

公开(公告)号：US06558980B2

公开(公告)日：2003-05-06

申请号：US09832008

申请日：2001-04-11

Applicant: Yoshinori Miyaki ,  Hiromichi Suzuki ,  Kazunari Suzuki ,  Takafumi Nishita ,  Fujio Ito ,  Kunihiro Tsubosaki ,  Akihiko Kameoka ,  Kunihiko Nishi

Inventor： Yoshinori Miyaki ,  Hiromichi Suzuki ,  Kazunari Suzuki ,  Takafumi Nishita ,  Fujio Ito ,  Kunihiro Tsubosaki ,  Akihiko Kameoka ,  Kunihiko Nishi

IPC: H01L2144

CPC classification number: H01L24/32 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49503 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/06179 ,  H01L2224/29007 ,  H01L2224/32014 ,  H01L2224/32055 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/48647 ,  H01L2224/48699 ,  H01L2224/48747 ,  H01L2224/48799 ,  H01L2224/48847 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2224/85447 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/01026 ,  H01L2924/3512 ,  H01L2924/00012

Abstract: A process is provided for the fabrication of a plastic molded type semiconductor device in which a die pad is formed to have a smaller area than a semiconductor chip to be mounted on a principal surface of the die pad and the semiconductor chip and die pad are sealed with a plastic mold. The semiconductor chip and the die pad are disposed within a cavity of a mold so that the clearance from the reverse surface of the die pad to the inside wall surface of the cavity opposite to the reverse surface of the die pad becomes narrower, by a length corresponding to the thickness of the die pad, than the clearance from the principal surface of the semiconductor chip to the inside wall surface of the cavity opposite to the principal surface of the semiconductor chip; and a resin is poured from a center gate into said cavity to form a plastic mold, which makes it possible to prevent said semiconductor chip from being lifted upwardly by the resin flowing in a filling region on the reverse surface side of the semiconductor chip. As a result, inconvenient shifting of the semiconductor chip, bonding wires and the like in the plastic mold can be prevented, leading to an increase in the yield of the plastic molded type semiconductor device.