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    Method and apparatus for real time two dimensional redundancy allocation
    1.
    发明授权
    Method and apparatus for real time two dimensional redundancy allocation 失效
    用于实时二维冗余分配的方法和装置

    公开(公告)号：US6026505A

    公开(公告)日：2000-02-15

    申请号：US777877

    申请日：1991-10-16

    申请人： Erik Leigh Hedberg ,  Garrett Stephen Koch

    发明人： Erik Leigh Hedberg ,  Garrett Stephen Koch

    IPC分类号： G06F12/16 ,  G11C29/00 ,  G11C29/04 ,  G11C29/12 ,  G11C29/44 ,  G11C29/56 ,  G06F11/00

    CPC分类号： G11C29/72 ,  G11C29/44

    摘要： A method and apparatus are provided in an array built in self test (ABIST) environment formed on a semiconductor chip having an array of memory cells arranged in columns and rows and column and row redundant lines which includes testing the array along the columns to identify a given number of faulty cells in each of the columns, storing the column addresses having the given number of faulty cells in first registers, further testing the array along the columns or rows to identify any additional faulty cells while masking the cells having the stored column addresses and storing the row addresses having the faulty cell in second registers until all of the second registers store row addresses, and after all of the second registers store row addresses, continue testing the array while masking the cells having the stored column or row addresses and storing the column addresses of any remaining additional faulty cell in any unused register of the first registers.

    摘要翻译： 一种方法和装置被提供在一个内置在自检（ABIST）环境中的阵列中，该阵列形成在半导体芯片上，该半导体芯片具有排列成列和行的存储单元阵列以及列和行冗余线，其包括沿着列测试阵列以识别 给定数量的每个列中的故障单元，将具有给定数量的故障单元的列地址存储在第一寄存器中，进一步沿列或行测试该阵列以识别任何附加的故障单元，同时掩蔽具有存储的列地址的单元 并且将具有故障单元的行地址存储在第二寄存器中，直到所有第二寄存器存储行地址，并且在所有第二寄存器存储行地址之后，继续测试阵列，同时屏蔽具有存储的列或行地址的单元并存储 第一个寄存器的任何未使用的寄存器中任何剩余的附加故障单元的列地址。

    Method and apparatus for real time two dimensional redundancy allocation
    2.
    发明授权
    Method and apparatus for real time two dimensional redundancy allocation 失效

    公开(公告)号：US5859804A

    公开(公告)日：1999-01-12

    申请号：US938757

    申请日：1997-09-26

    申请人： Erik Leigh Hedberg ,  Garrett Stephen Koch

    发明人： Erik Leigh Hedberg ,  Garrett Stephen Koch

    IPC分类号： G06F12/16 ,  G11C29/00 ,  G11C29/04 ,  G11C29/12 ,  G11C29/44 ,  G11C29/56 ,  G11C7/00

    CPC分类号： G11C29/72 ,  G11C29/44

    摘要： A method and apparatus are provided in an array built in self test (ABIST) environment formed on a semiconductor chip having an array of memory cells arranged in columns and rows and column and row redundant lines which includes testing the array along the columns to identify a given number of faulty cells in each of the columns, storing the column addresses having the given number of faulty cells in first registers, further testing the array along the columns or rows to identify any additional faulty cells while masking the cells having the stored column addresses and storing the row addresses having the faulty cell in second registers until all of the second registers store row addresses, and after all of the second registers store row addresses, continue testing the array while masking the cells having the stored column or row addresses and storing the column addresses of any remaining additional faulty cell in any unused register of the first registers.

    Methods for fabricating multichip semiconductor structures with consolidated circuitry and programmable ESD protection for input/output nodes
    4.
    发明授权
    Methods for fabricating multichip semiconductor structures with consolidated circuitry and programmable ESD protection for input/output nodes 失效
    用于制造具有合并电路的多芯片半导体结构和用于输入/输出节点的可编程ESD保护的方法

    公开(公告)号：US5807791A

    公开(公告)日：1998-09-15

    申请号：US785032

    申请日：1997-01-02

    申请人： Claude Louis Bertin ,  Erik Leigh Hedberg ,  James Marc Leas ,  Steven Howard Voldman

    发明人： Claude Louis Bertin ,  Erik Leigh Hedberg ,  James Marc Leas ,  Steven Howard Voldman

    IPC分类号： H01L23/528 ,  H01L23/60 ,  H01L25/065 ,  H01L27/02 ,  G11C5/06

    CPC分类号： H01L23/5286 ,  H01L23/60 ,  H01L25/0657 ,  H01L27/0251 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2924/0002 ,  H01L2924/3011

    摘要： Multichip semiconductor structures with consolidated circuitry are disclosed, along with programmable electrostatic discharge (ESD) protection circuits for chip input/output (I/O) nodes. The multichip structures include a first semiconductor chip having a first circuit at least partially providing a first predetermined circuit function, and a second semiconductor chip electrically and mechanically coupled to the first semiconductor chip. The second semiconductor device chip has a second circuit that at least partially provides a circuit function to the first circuit of the first semiconductor chip. In one embodiment, the first semiconductor chip comprises a memory array chip, while the second semiconductor chip comprises a logic chip wherein at least some peripheral circuitry necessary for accessing the memory array of the memory array chip resides within the logic chip. This allows the removal of redundant circuitry from identical chips of a multichip structure. Also disclosed is removing, adding or balancing ESD circuit loading on input/output nodes of a multichip stack. Various techniques are presented for selective removal of ESD circuitry from commonly connected I/O nodes. Any circuitry interfacing with an external device may be rebalanced at the multichip level using this concept.

    摘要翻译： 公开了具有整合电路的多芯片半导体结构，以及用于芯片输入/输出（I / O）节点的可编程静电放电（ESD）保护电路。 多芯片结构包括具有至少部分地提供第一预定电路功能的第一电路的第一半导体芯片，以及电和机械耦合到第一半导体芯片的第二半导体芯片。 第二半导体器件芯片具有至少部分地向第一半导体芯片的第一电路提供电路功能的第二电路。 在一个实施例中，第一半导体芯片包括存储器阵列芯片，而第二半导体芯片包括逻辑芯片，其中访问存储器阵列芯片的存储器阵列所需的至少一些外围电路驻留在逻辑芯片内。 这允许从多芯片结构的相同芯片去除冗余电路。 还公开了在多芯片堆叠的输入/输出节点上移除，添加或平衡ESD电路负载。 提出了各种技术，用于从共同连接的I / O节点选择性地去除ESD电路。 与外部设备接口的任何电路可以使用这个概念在多芯片级别重新平衡。

    Input port switching protocol for a random access memory
    5.
    发明授权
    Input port switching protocol for a random access memory 失效
    用于随机存取存储器的输入端口切换协议

    公开(公告)号：US5898623A

    公开(公告)日：1999-04-27

    申请号：US947762

    申请日：1997-10-09

    申请人： Michael Patrick Clinton ,  Timothy Jay Dell ,  Erik Leigh Hedberg ,  Mark William Kellogg ,  Wilbur David Pricer

    发明人： Michael Patrick Clinton ,  Timothy Jay Dell ,  Erik Leigh Hedberg ,  Mark William Kellogg ,  Wilbur David Pricer

    IPC分类号： G11C7/10 ,  G11C16/04

    CPC分类号： G11C7/1072 ,  G11C7/1006

    摘要： A high speed/narrow I/O DRAM device comprises both a data input/output (I/O) port as well as a command port for receiving commands used to control the operations of the DRAM. The command port is defined as input only (i.e., for inputting command data). The present invention comprises multiplexing write data to be written and stored in the DRAM onto the command port with command data packets. The data I/O port can then become dedicated to streaming out seamless data since it no longer needs to flip between input and output data. Even greater bus efficiency can be realized if, during a command packet transfer, data writes to the DRAM are switched back to the data I/O port. With this input port switching protocol, greater bus efficiency and increased memory performance can be realized.

    摘要翻译： 高速/窄I / O DRAM装置包括数据输入/输出（I / O）端口以及用于接收用于控制DRAM操作的命令的命令端口。 命令端口被定义为仅输入（即，用于输入命令数据）。 本发明包括将要写入和存储在DRAM中的写入数据复用到具有命令数据分组的命令端口上。 然后，数据I / O端口可以专用于流出无缝数据，因为它不再需要在输入和输出数据之间翻转。 如果在命令包传送期间，将数据写入DRAM切换回数据I / O端口，则可以实现更大的总线效率。 通过该输入端口切换协议，可以实现更高的总线效率和更高的存储器性能。

    Memory device with programmable self-refreshing and testing methods therefore
    10.
    发明授权
    Memory device with programmable self-refreshing and testing methods therefore 失效
    因此，具有可编程自刷新和测试方法的存储器件

    公开(公告)号：US5703823A

    公开(公告)日：1997-12-30

    申请号：US435606

    申请日：1995-05-05

    申请人： David Elson Douse ,  Wayne Frederick Ellis ,  Erik Leigh Hedberg

    发明人： David Elson Douse ,  Wayne Frederick Ellis ,  Erik Leigh Hedberg

    IPC分类号： G11C11/401 ,  G11C11/403 ,  G11C11/406 ,  G11C29/00 ,  G11C29/02 ,  G11C29/08 ,  G11C29/14 ,  G11C7/00

    CPC分类号： G11C11/406 ,  G11C29/02

    摘要： A programmable self-time refresh circuit for a semiconductor memory and methods for programming the self-refresh rate for non-invasively and deterministically testing the self-timed refresh circuit for establishing/verifying a refresh rate and a wait state interval for the self-refresh operation. The programmable refresh circuit includes a self-timed oscillator that outputs a clocking signal, and a programmable pattern generator that outputs a first signal pattern and a second signal pattern. The first signal pattern is fed to a counter circuit which also receives the clocking signal. The counter circuit outputs a signal pulse whenever the count driven by the clocking signal reaches a digital pattern representation corresponding to the first signal pattern generated by the programmable pattern generator. Refresh control logic is connected to receive the pulse signal and respond thereto by refreshing a portion of the memory array of the semiconductor memory device. The second signal pattern is employed by the refresh control logic to set the wait state interval for the self-refresh operation. Multiple methods for testing the programmable self-refresh circuit are also set forth.

    摘要翻译： 一种用于半导体存储器的可编程自适应刷新电路以及用于非侵入式地编程自刷新率的方法，并且确定地测试用于建立/验证刷新率的自定时刷新电路和用于自刷新的等待状态间隔 操作。 可编程刷新电路包括输出时钟信号的自定时振荡器和输出第一信号模式和第二信号模式的可编程模式发生器。 第一信号模式被馈送到还接收时钟信号的计数器电路。 每当由时钟信号驱动的计数达到对应于可编程模式发生器产生的第一信号模式的数字模式表示时，计数器电路输出信号脉冲。 连接刷新控制逻辑以接收脉冲信号并通过刷新半导体存储器件的存储器阵列的一部分来对其进行响应。 刷新控制逻辑采用第二信号模式来设置自刷新操作的等待状态间隔。 还阐述了用于测试可编程自刷新电路的多种方法。