公开(公告)号：US20080294950A1

公开(公告)日：2008-11-27

申请号：US12188033

申请日：2008-08-07

申请人： Luiz Carlos Alves ,  Mark Andrew Brittain ,  Timothy Jay Dell ,  Sanjeev Ghai ,  Warren Edward Maule ,  Scott Barnett Swaney

发明人： Luiz Carlos Alves ,  Mark Andrew Brittain ,  Timothy Jay Dell ,  Sanjeev Ghai ,  Warren Edward Maule ,  Scott Barnett Swaney

IPC分类号： G11C29/04 ,  G06F11/22

CPC分类号： G11C29/42 ,  G06F11/1044 ,  G11C5/04 ,  G11C29/4401 ,  G11C29/76 ,  G11C29/846 ,  G11C2029/0409

摘要： A method and system is presented for correcting a data error in a primary Dynamic Random Access Memory (DRAM) in a Dual In-line Memory Module (DIMM). Each DRAM has a left half (for storing bits 0:3) and a right half (for storing bits 4:7). A determination is made as to whether the data error was in the left or right half of the primary DRAM. The half of the primary DRAM in which the error occurred is removed from service. All subsequent reads and writes for data originally stored in the primary DRAM's defective half are made to a half of a spare DRAM in the DIMM, while the DRAM's non-defective half continues to be used for subsequently storing data.

摘要翻译： 提出了一种用于校正双列直插式存储器模块（DIMM）中的主动态随机存取存储器（DRAM）中的数据错误的方法和系统。 每个DRAM具有左半部分（用于存储位0：3）和右半部分（用于存储位4：7）。 确定数据错误是在主DRAM的左半还是右半部。 发生错误的主要DRAM的一半从服务中删除。 原始存储在主DRAM缺陷半部分的数据的所有后续读取和写入都被制成DIMM中的备用DRAM的一半，而DRAM的无缺陷半部分继续用于随后存储数据。

公开(公告)号：US6111757A

公开(公告)日：2000-08-29

申请号：US7941

申请日：1998-01-16

申请人： Timothy Jay Dell ,  Mark William Kellogg ,  Bruce Gerard Hazelzet

发明人： Timothy Jay Dell ,  Mark William Kellogg ,  Bruce Gerard Hazelzet

IPC分类号： H01L27/10 ,  G11C5/00 ,  G11C5/06 ,  G11C8/12 ,  G11C11/401 ,  H05K1/11

CPC分类号： H05K1/117 ,  G11C5/06 ,  G11C8/12 ,  H05K1/0295 ,  H05K2201/09954 ,  H05K2201/10166

摘要： A memory module configured such that it can be operated as a first memory module such as a (Single In-line Memory Module) SIMM or as a second memory module such as a (Dual In-linc Memory Module) DIMM module without requiring external switching circuitry. This is accomplished by providing a memory module card with a circuit thereon that is designed to emulate a DIMM module when plugged into a DIMM socket as found in the latest computer architectures and to emulate a SIMM module when plugged into a SIMM socket as found in older computer architectures. The memory module is provided with memory devices (DRAMS or SDRAMS) and interconnecting bypass devices (CMOS transistor pairs) mounted thereon. The bypass devices and are also connected to terminal pads adjacent the first and second edges of the module, such that upon insertion of a first edge into a mating DIMM socket, the bypass devices are activated to interconnect the memory devices as, for example, a 1 bank 168 pin DIMM and upon insertion of the second edge into a SIMM socket, the memory devices are interconnected as, for example, a 2 bank 72 pin SIMM. The present invention decreases the need for manufacturing and maintaining separate SIMM and DIMM inventories and provides the capability of extending and expanding existing computer systems if the memory modules or cards originally designed for the computer are deleted from future inventories or become prohibitively expensive or difficult to locate.

摘要翻译： 一种存储器模块，其被配置为使得其可以作为第一存储器模块（诸如（单列直插式存储器模块）SIMM）或作为第二存储器模块（例如（双In-linc存储器模块）DIMM模块）而不需要外部切换 电路。 这通过在其上提供具有电路的存储器模块卡来实现，该存储器模块卡被设计成当插入到最新计算机体系结构中的DIMM插槽中时模拟DIMM模块，并且当插入到SIMM插座中时模拟SIMM模块，如在旧的 电脑架构。 存储器模块具有安装在其上的存储器件（DRAMS或SDRAMS）和互连旁路器件（CMOS晶体管对）。 旁路装置并且还连接到邻近模块的第一和第二边缘的端子焊盘，使得当将第一边缘插入到配合的DIMM插槽中时，旁路装置被激活以将存储器装置互连，例如， 1组168针DIMM，并且当将第二边缘插入SIMM插座时，存储器件例如被连接到2组72针SIMM。 本发明减少了制造和维护单独的SIMM和DIMM清单的需要，并提供扩展和扩展现有计算机系统的能力，如果最初为计算机设计的存储器模块或卡从将来的存货中删除或变得昂贵或难以定位 。

公开(公告)号：US06097883A

公开(公告)日：2000-08-01

申请号：US889263

申请日：1997-07-08

申请人： Timothy Jay Dell ,  Mark William Kellogg ,  Bruce Gerard Hazelzet

发明人： Timothy Jay Dell ,  Mark William Kellogg ,  Bruce Gerard Hazelzet

IPC分类号： G11C5/00 ,  H05K1/11 ,  G06F13/00

CPC分类号： G11C5/06 ,  G11C5/04 ,  G11C8/12 ,  H05K1/117

摘要： A printed circuit card having first and second circuit units mounted thereon in connection to terminal pads adjacent two card edges, with the first and second circuit units being in connection to each other and to select pads of a first edge such that upon insertion of that edge into a given card socket, both circuit units are enabled, and the circuit units also being in connection to the pads of a second edge such that upon insertion of that edge into a second card socket, only the second circuit unit is enabled. In the preferred embodiment, the card is a memory module card having buffer and memory circuit units designed to cooperate with each other and with either of standard, buffered or unbuffered memory card sockets in a system board in accordance with insertion of a first or second pad edge in one of the card sockets to automatically provide, either combined circuit unit operation, or single circuit operation. The invention is also applicable to clocked register circuits and series pass devices.

摘要翻译： 一种印刷电路卡，其具有安装在其上的第一和第二电路单元，其连接到与两个卡边缘相邻的端子焊盘，其中第一和第二电路单元彼此连接并选择第一边缘的焊盘，使得在插入该边缘 在给定的卡插座中，两个电路单元被使能，并且电路单元也与第二边缘的焊盘连接，使得当将该边缘插入到第二卡插槽中时，仅启用第二电路单元。 在优选实施例中，卡是具有缓冲器和存储器电路单元的存储器模块卡，该缓冲器和存储器电路单元被设计为根据第一或第二焊盘的插入而相互配合并且与系统板中的标准缓冲或非缓冲存储卡插槽 在其中一个卡插槽中自动提供组合电路单元操作或单电路操作。 本发明也适用于时钟寄存器电路和串行通道器件。

公开(公告)号：US5996096A

公开(公告)日：1999-11-30

申请号：US749583

申请日：1996-11-15

申请人： Timothy Jay Dell ,  Mark William Kellogg

发明人： Timothy Jay Dell ,  Mark William Kellogg

IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G01R31/28

CPC分类号： G11C29/816 ,  G11C29/88

摘要： Reduced specification DRAMs are used in memory assemblies in such a way as to maximize the use of the good cells in the reduced specification DRAM chips. An external memory array is mapped to replace defective memory locations on a real time basis. The major components are (1) a non-volatile storage device, (2) a logic device, and (3) a volatile storage device. The non-volatile storage device, such as an EPROM, EEPROM, or a flash memory chip, is used to retain address information for all memory fails on a given assembly. In simpler implementations, the use of specific combinations of RAM failure types can be used in addition to a logic decode chip, with the raw card identifying to the decode chip the failing address information (via solder jumpers). The logic device is an ASIC or programmable logic device which contains the bit steering logic and timing generation logic to redirect defective RAM addresses to an alternate storage device for all read and write operations. The volatile storage device is a RAM array that is used to replace failing address locations in the original reduced specification memory. This array may be in the form a static random access memory (SRAM or DRAM) array, resident in the logic device described above. The size of the device determines the amount of failing addresses that can be allowed in the reduced specification memory.

摘要翻译： 减少的规格DRAM以这样的方式用于存储器组件中，以便最大限度地减少规范DRAM芯片中的良好单元的使用。 外部存储器阵列被映射以实时替代有缺陷的存储器位置。 主要部件为（1）非易失性存储装置，（2）逻辑装置，（3）易失性存储装置。 使用诸如EPROM，EEPROM或闪速存储器芯片的非易失性存储设备来保留给定组件上的所有存储器的地址信息失效。 在更简单的实现中，除了逻辑解码芯片之外，还可以使用RAM故障类型的特定组合，原始卡将解码芯片识别出故障地址信息（通过焊接跳线）。 逻辑器件是ASIC或可编程逻辑器件，其包含位转向逻辑和定时产生逻辑，用于将有缺陷的RAM地址重定向到用于所有读和写操作的备用存储器件。 易失性存储设备是用于替换原始缩小规范存储器中的故障地址位置的RAM阵列。 该阵列可以是驻留在上述逻辑设备中的静态随机存取存储器（SRAM或DRAM）阵列的形式。 设备的大小决定了在缩小的规范存储器中允许的故障地址的数量。

公开(公告)号：US5745914A

公开(公告)日：1998-04-28

申请号：US770924

申请日：1996-12-20

申请人： Brian J. Connolly ,  Timothy Jay Dell ,  Bruce Gerard Hazelzet ,  Mark William Kellogg

发明人： Brian J. Connolly ,  Timothy Jay Dell ,  Bruce Gerard Hazelzet ,  Mark William Kellogg

IPC分类号： G06F12/02 ,  G06F12/00 ,  G06F12/06 ,  G11C7/22 ,  G11C8/18 ,  G11C11/401 ,  G11C11/406

CPC分类号： G11C7/22 ,  G11C11/406 ,  G11C8/18

摘要： A method and logic circuit are provided which method and logic circuit allow both a CBR and hidden refresh to take place on DRAM's populating SIMM's or DIMM's, wherein both a single system RAS and single system CAS are converted to multiple RAS's and multiple CAS's for normal read/write operation on the DRAM's.

摘要翻译： 提供了一种方法和逻辑电路，该方法和逻辑电路允许在DRAM的填充SIMM或DIMM上进行CBR和隐藏刷新，其中单个系统RAS和单个系统CAS都被转换为多个RAS和多个CAS用于正常读取 /对DRAM的写操作。

公开(公告)号：US5881072A

公开(公告)日：1999-03-09

申请号：US673404

申请日：1996-06-28

申请人： Timothy Jay Dell

发明人： Timothy Jay Dell

IPC分类号： G06F11/10 ,  G06F11/00

CPC分类号： G06F11/1048

摘要： According to the preferred embodiment, a method is provided to electronically detect the presence of error correcting memory modules in a computer system in an easy and efficient manner. The method forces an error in the memory system and detects whether there is an error reporting output on the error active line. In the preferred method, the memory refresh for the memory system is turned off for a period of time sufficient to introduce errors in the memory. Then, a read is done while monitoring the error active line. If any bank of memory has an error line active go active during a read, than an error correcting memory module is installed. If not, than a standard memory module is installed.

摘要翻译： 根据优选实施例，提供了一种以简单和有效的方式电子地检测计算机系统中纠错存储器模块的存在的方法。 该方法会强制存储系统中的错误，并检测错误活动行是否有错误报告输出。 在优选的方法中，存储器系统的存储器刷新被关闭足以在存储器中引入错误的时间段。 然后，在监视错误活动行时进行读取。 如果存储器中的任何一行存在错误行有效，则在读取期间将被激活，而不是安装错误纠正内存模块。 如果没有，则安装标准内存模块。

公开(公告)号：US06445744B1

公开(公告)日：2002-09-03

申请号：US09224825

申请日：1999-01-04

申请人： Timothy Jay Dell ,  Wilbur David Pricer

发明人： Timothy Jay Dell ,  Wilbur David Pricer

IPC分类号： H04K110

CPC分类号： H04L25/0272 ,  H04L25/0292 ,  H04L25/14

摘要： A highspeed bus architecture featuring low signal levels, differential sensing, and zero net current over a four wire transmission line cluster. The bus system comprises a system for transmitting n bits of data and includes an encoding system for receiving the n bits of data and outputting m signals wherein the m signals have a zero net current, m transmission lines for carrying the m signals, and a decoding system for receiving the m signals and converting the m signals back into n bits of data, using differential amplifiers.

摘要翻译： 高速总线架构，具有低信号电平，差分感测和四线传输线集群的零净电流。 总线系统包括用于发送n位数据的系统，并且包括用于接收n位数据并输出m个信号的编码系统，其中m个信号具有零净电流，m个用于承载m个信号的传输线，以及解码 系统，用于接收m个信号，并使用差分放大器将m个信号转换回n位数据。

公开(公告)号：US06173382B2

公开(公告)日：2001-01-09

申请号：US09067420

申请日：1998-04-28

申请人： Timothy Jay Dell ,  Mark William Kellogg

发明人： Timothy Jay Dell ,  Mark William Kellogg

IPC分类号： G06F1200

CPC分类号： G11C5/06 ,  G06F13/1694 ,  G11C7/1045

摘要： A memory module includes a plurality of memory chips on the module; first logic for configuring the memory module to operate in a selectable mode; second logic for storing initial presence detect (PD) data; and third logic for storing modified PD data that corresponds to a requested mode of operation of the memory module received from a system controller.

摘要翻译： 存储模块包括在模块上的多个存储器芯片; 用于配置存储器模块以可选择模式操作的第一逻辑; 用于存储初始存在检测（PD）数据的第二逻辑; 以及用于存储对应于从系统控制器接收的存储器模块的所请求的操作模式的修改的PD数据的第三逻辑。

公开(公告)号：US6044483A

公开(公告)日：2000-03-28

申请号：US15874

申请日：1998-01-29

申请人： Chin-Long Chen ,  Timothy Jay Dell ,  Wayne C. Kwan

发明人： Chin-Long Chen ,  Timothy Jay Dell ,  Wayne C. Kwan

IPC分类号： H03M13/15 ,  H03M13/00

CPC分类号： H03M13/13 ,  G06F11/1044 ,  H03M13/6575

摘要： A method and apparatus are described for providing error correcting code (ECC) which may be incorporated into a computer system which includes one of a plurality of memory configurations and which may include a pre-existing error control feature. A data store operation causes the receipt of a word including data bits and check bits generated by a pre-existing error control feature. The data and check bits of the received word are used to generate additional check bits based upon the configuration of the computer system memory. The additionally generated check bits are stored in the memory along with the received word. Upon a subsequent data fetch operation which retrieves the word and check bits the check bits are decoded thereby providing error detection and correction in the retrieved word for single and multiple bit errors including the failure of an entire memory chip. The invention provides 84/72 ECC for computer systems having a four bit per chip memory configuration and 88/72 ECC for computer systems having an eight bit per chip memory configuration. Further embodiments provide downstream error notification propagation for the host computer system.

摘要翻译： 描述了一种用于提供纠错码（ECC）的方法和装置，该纠错码可以被并入到包括多个存储器配置中的一个并且可以包括预先存在的错误控制特征的计算机系统中。 数据存储操作使得包含数据位和由先前存在的错误控制特征产生的校验位的字的接收。 接收到的字的数据和校验位用于根据计算机系统存储器的配置产生附加校验位。 附加生成的校验位与所接收的字一起存储在存储器中。 在随后的检索字和检查位的数据提取操作中，校验位被解码，从而在包括整个存储器芯片的故障的单个和多个位错误的检索到的字中提供错误检测和校正。 本发明为具有每位芯片存储器配置的4位的计算机系统提供84/72 ECC，并且具有每个芯片存储器配置具有8位的计算机系统的88/72 ECC。 另外的实施例为主计算机系统提供下游错误通知传播。

公开(公告)号：US6044479A

公开(公告)日：2000-03-28

申请号：US15134

申请日：1998-01-29

申请人： Timothy Jay Dell

发明人： Timothy Jay Dell

IPC分类号： G06F11/10 ,  G06F11/32 ,  G06F11/00

CPC分类号： G06F11/1044 ,  G06F11/326

摘要： A method and apparatus are described for providing a human sensorially significant indication of the occurrence of a sequence of error events in an ECC system as they occur over time. Each error indication element is kept activated for a human sensorially significant ("HSS") time interval which is tracked by maintaining a count of refresh pulses received from a memory system. A HSS interval timer includes a D-type flip flop which pulses a binary counter for each refresh operation. The counter, when full, produces a reset signal. An error indication signal from an ECC system is provided to a error condition latch which activates a sensorial error indicator element if the error indication signal is provided to the latch while the memory system is performing a memory read operation. The latch is subsequently reset by the reset signal from the counter after a HSS interval has transpired. Further embodiments provide separate HSS indications for single and multiple bit errors as well as a static indication of the detection of an uncorrectable error.

摘要翻译： 描述了一种方法和装置，用于在ECC系统随着时间的推移发生时，提供对ECC系统中的一系列错误事件的发生的人的感知有意义的指示。 每个错误指示元件被保持激活以通过维持从存储器系统接收到的刷新脉冲的计数来跟踪的人感知有意义（“HSS”）时间间隔。 HSS间隔定时器包括D型触发器，其针对每个刷新操作脉冲二进制计数器。 计数器在满时产生复位信号。 来自ECC系统的错误指示信号被提供给错误状态锁存器，该错误状态锁存器在存储器系统执行存储器读取操作时将错误指示信号提供给锁存器时激活感觉错误指示器元件。 在HSS间隔发生后，锁存器随后由来自计数器的复位信号复位。 另外的实施例提供单个和多个位错误的单独HSS指示以及检测不可校正错误的静态指示。