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    Methods for fabricating multichip semiconductor structures with consolidated circuitry and programmable ESD protection for input/output nodes
    5.
    发明授权
    Methods for fabricating multichip semiconductor structures with consolidated circuitry and programmable ESD protection for input/output nodes 失效
    用于制造具有合并电路的多芯片半导体结构和用于输入/输出节点的可编程ESD保护的方法

    公开(公告)号：US5807791A

    公开(公告)日：1998-09-15

    申请号：US785032

    申请日：1997-01-02

    申请人： Claude Louis Bertin ,  Erik Leigh Hedberg ,  James Marc Leas ,  Steven Howard Voldman

    发明人： Claude Louis Bertin ,  Erik Leigh Hedberg ,  James Marc Leas ,  Steven Howard Voldman

    IPC分类号： H01L23/528 ,  H01L23/60 ,  H01L25/065 ,  H01L27/02 ,  G11C5/06

    CPC分类号： H01L23/5286 ,  H01L23/60 ,  H01L25/0657 ,  H01L27/0251 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2924/0002 ,  H01L2924/3011

    摘要： Multichip semiconductor structures with consolidated circuitry are disclosed, along with programmable electrostatic discharge (ESD) protection circuits for chip input/output (I/O) nodes. The multichip structures include a first semiconductor chip having a first circuit at least partially providing a first predetermined circuit function, and a second semiconductor chip electrically and mechanically coupled to the first semiconductor chip. The second semiconductor device chip has a second circuit that at least partially provides a circuit function to the first circuit of the first semiconductor chip. In one embodiment, the first semiconductor chip comprises a memory array chip, while the second semiconductor chip comprises a logic chip wherein at least some peripheral circuitry necessary for accessing the memory array of the memory array chip resides within the logic chip. This allows the removal of redundant circuitry from identical chips of a multichip structure. Also disclosed is removing, adding or balancing ESD circuit loading on input/output nodes of a multichip stack. Various techniques are presented for selective removal of ESD circuitry from commonly connected I/O nodes. Any circuitry interfacing with an external device may be rebalanced at the multichip level using this concept.

    摘要翻译： 公开了具有整合电路的多芯片半导体结构，以及用于芯片输入/输出（I / O）节点的可编程静电放电（ESD）保护电路。 多芯片结构包括具有至少部分地提供第一预定电路功能的第一电路的第一半导体芯片，以及电和机械耦合到第一半导体芯片的第二半导体芯片。 第二半导体器件芯片具有至少部分地向第一半导体芯片的第一电路提供电路功能的第二电路。 在一个实施例中，第一半导体芯片包括存储器阵列芯片，而第二半导体芯片包括逻辑芯片，其中访问存储器阵列芯片的存储器阵列所需的至少一些外围电路驻留在逻辑芯片内。 这允许从多芯片结构的相同芯片去除冗余电路。 还公开了在多芯片堆叠的输入/输出节点上移除，添加或平衡ESD电路负载。 提出了各种技术，用于从共同连接的I / O节点选择性地去除ESD电路。 与外部设备接口的任何电路可以使用这个概念在多芯片级别重新平衡。

    Method and apparatus for real time two dimensional redundancy allocation
    7.
    发明授权
    Method and apparatus for real time two dimensional redundancy allocation 失效

    公开(公告)号：US5859804A

    公开(公告)日：1999-01-12

    申请号：US938757

    申请日：1997-09-26

    申请人： Erik Leigh Hedberg ,  Garrett Stephen Koch

    发明人： Erik Leigh Hedberg ,  Garrett Stephen Koch

    IPC分类号： G06F12/16 ,  G11C29/00 ,  G11C29/04 ,  G11C29/12 ,  G11C29/44 ,  G11C29/56 ,  G11C7/00

    CPC分类号： G11C29/72 ,  G11C29/44

    摘要： A method and apparatus are provided in an array built in self test (ABIST) environment formed on a semiconductor chip having an array of memory cells arranged in columns and rows and column and row redundant lines which includes testing the array along the columns to identify a given number of faulty cells in each of the columns, storing the column addresses having the given number of faulty cells in first registers, further testing the array along the columns or rows to identify any additional faulty cells while masking the cells having the stored column addresses and storing the row addresses having the faulty cell in second registers until all of the second registers store row addresses, and after all of the second registers store row addresses, continue testing the array while masking the cells having the stored column or row addresses and storing the column addresses of any remaining additional faulty cell in any unused register of the first registers.

    Memory device with programmable self-refreshing and testing methods therefore
    8.
    发明授权
    Memory device with programmable self-refreshing and testing methods therefore 失效
    因此，具有可编程自刷新和测试方法的存储器件

    公开(公告)号：US5703823A

    公开(公告)日：1997-12-30

    申请号：US435606

    申请日：1995-05-05

    申请人： David Elson Douse ,  Wayne Frederick Ellis ,  Erik Leigh Hedberg

    发明人： David Elson Douse ,  Wayne Frederick Ellis ,  Erik Leigh Hedberg

    IPC分类号： G11C11/401 ,  G11C11/403 ,  G11C11/406 ,  G11C29/00 ,  G11C29/02 ,  G11C29/08 ,  G11C29/14 ,  G11C7/00

    CPC分类号： G11C11/406 ,  G11C29/02

    摘要： A programmable self-time refresh circuit for a semiconductor memory and methods for programming the self-refresh rate for non-invasively and deterministically testing the self-timed refresh circuit for establishing/verifying a refresh rate and a wait state interval for the self-refresh operation. The programmable refresh circuit includes a self-timed oscillator that outputs a clocking signal, and a programmable pattern generator that outputs a first signal pattern and a second signal pattern. The first signal pattern is fed to a counter circuit which also receives the clocking signal. The counter circuit outputs a signal pulse whenever the count driven by the clocking signal reaches a digital pattern representation corresponding to the first signal pattern generated by the programmable pattern generator. Refresh control logic is connected to receive the pulse signal and respond thereto by refreshing a portion of the memory array of the semiconductor memory device. The second signal pattern is employed by the refresh control logic to set the wait state interval for the self-refresh operation. Multiple methods for testing the programmable self-refresh circuit are also set forth.

    摘要翻译： 一种用于半导体存储器的可编程自适应刷新电路以及用于非侵入式地编程自刷新率的方法，并且确定地测试用于建立/验证刷新率的自定时刷新电路和用于自刷新的等待状态间隔 操作。 可编程刷新电路包括输出时钟信号的自定时振荡器和输出第一信号模式和第二信号模式的可编程模式发生器。 第一信号模式被馈送到还接收时钟信号的计数器电路。 每当由时钟信号驱动的计数达到对应于可编程模式发生器产生的第一信号模式的数字模式表示时，计数器电路输出信号脉冲。 连接刷新控制逻辑以接收脉冲信号并通过刷新半导体存储器件的存储器阵列的一部分来对其进行响应。 刷新控制逻辑采用第二信号模式来设置自刷新操作的等待状态间隔。 还阐述了用于测试可编程自刷新电路的多种方法。

    Impedance control using fuses
    9.
    发明授权
    Impedance control using fuses 有权
    使用熔断器进行阻抗控制

    公开(公告)号：US06243283B1

    公开(公告)日：2001-06-05

    申请号：US09589922

    申请日：2000-06-07

    申请人： Claude Louis Bertin ,  John A. Fifield ,  Erik Leigh Hedberg ,  Russell J. Houghton ,  Timothy Dooling Sullivan ,  Steven William Tomashot ,  William Robert Tonti

    发明人： Claude Louis Bertin ,  John A. Fifield ,  Erik Leigh Hedberg ,  Russell J. Houghton ,  Timothy Dooling Sullivan ,  Steven William Tomashot ,  William Robert Tonti

    IPC分类号： G11C506

    CPC分类号： H01L23/481 ,  G11C17/16 ,  H01L25/0657 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/48227 ,  H01L2224/4826 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2225/06596 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/15192 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012

    摘要： A system and method for reducing impedance loading of semiconductor integrated circuit devices implementing protective device structures that contributes to impedance loading at an I/O pad connection. The method comprises providing a fuse device between the I/O pad connection and the protective device; connecting a current source device associated with each fuse device in the integrated circuit, the current source device connected to one end of the fuse device; providing fuse selection circuit for activating current flow through a selected fuse device between the current source and the I/O connection, the current flow being of an amount sufficient for blowing the fuse and disconnecting the protective device from the circuit structure, thereby reducing impedance loading at the I/O connection. Such a system and method is employed in a memory system comprising integrated circuit chips disposed in a stacked relation, with each chip including: a layer of active circuitry formed at a first layer of each chip; a plurality of through conducting structures disposed substantially vertically through each chip for enabling electronic connection with active circuitry at the first layer; second conducting device disposed at an end of the through conducting structure at an opposite side of a chip for connection with a corresponding through conductive structure of an adjacent stacked chip, the stacked chip structure formed by aligning one or more through conducting structures and second conducting devices of adjacent chips, whereby a chip of the stack is electronically connected to active circuitry formed on other chips of the stack. The stacked chip structure is ideal for reducing data access latency in memory systems employing memory chips such as DRAM.

    摘要翻译： 一种用于减少半导体集成电路器件的阻抗负载的系统和方法，其实现了有助于I / O焊盘连接处的阻抗加载的保护器件结构。 该方法包括在I / O焊盘连接和保护装置之间设置熔丝装置; 连接与所述集成电路中的每个熔丝装置相关联的电流源装置，所述电流源装置连接到所述熔丝装置的一端; 提供保险丝选择电路，用于在电流源和I / O连接之间激活通过选定的保险丝装置的电流流动，电流量足以吹入保险丝并将保护装置与电路结构断开，从而减少阻抗负载 在I / O连接。 这种系统和方法被用在包括以堆叠关系布置的集成电路芯片的存储器系统中，每个芯片包括：形成在每个芯片的第一层的有源电路层; 多个通过导电结构，其基本垂直设置穿过每个芯片，以使得能够与第一层处的有源电路电连接; 第二导电装置，其设置在通孔导电结构的与芯片相对侧的端部处，与相邻的堆叠芯片的相应的贯穿导电结构相连接，所述堆叠的芯片结构通过将一个或多个穿过导电结构和第二导电装置 的相邻芯片，由此堆叠的芯片电连接到形成在堆叠的其他芯片上的有源电路。 堆叠式芯片结构非常适用于采用诸如DRAM之类的存储器芯片的存储器系统中的数据访问延迟。

    Chip thermal protection device
    10.
    发明授权
    Chip thermal protection device 有权
    芯片热保护装置

    公开(公告)号：US06219215B1

    公开(公告)日：2001-04-17

    申请号：US09303042

    申请日：1999-04-30

    申请人： Claude Louis Bertin ,  Erik Leigh Hedberg ,  Timothy Dooling Sullivan ,  William Robert Tonti

    发明人： Claude Louis Bertin ,  Erik Leigh Hedberg ,  Timothy Dooling Sullivan ,  William Robert Tonti

    IPC分类号： H02H300

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  Y10T307/25 ,  H01L2924/00

    摘要： A gap conducting structure for an integrated electronic circuit that functions as an electronic fuse device and that is integrated as part of the semi-conductor chip wiring for providing over-current and thermal runaway protection. The gap conducting structure includes one or more air gap regions of predefined volume that fully or partially exposes a length of interlevel conductor layer in an IC. Alternately, the air gap region may wholly located within the dielectric region below a corresponding conductor and separated by insulator. When functioning as a fuse, the gap region acts to reduce thermal conductivity away from the exposed portion of the conductor enabling generation of higher heat currents in the conducting line with lower applied voltages sufficient to destruct a part of the partially exposed/fully exposed conducting line, thus preventing thermal runaway and over-current condition. The presence of gaps, and hence, the fuses, are scalable and may be tailored to the capacity of currents they must carry with the characteristics of the fuses defined by a circuit designer.

    摘要翻译： 用作集成电子电路的间隙导电结构，其用作电子熔断器件，并且被集成为用于提供过电流和热失控保护的半导体芯片布线的一部分。 间隙导电结构包括一个或多个预定体积的气隙区域，其完全或部分地暴露IC中的层间导体层的长度。 或者，气隙区域可以完全位于相应导体下方的电介质区域内并被绝缘体分隔开。 当用作熔丝时，间隙区域用于降低远离导体的暴露部分的热导率，使得能够以较低的施加电压在导电线中产生更高的热流，足以破坏部分暴露/完全暴露的导电线的一部分 ，从而防止热失控和过电流状态。 间隙的存在以及保险丝的存在是可扩展的，并且可以根据电路设计者定义的保险丝的特性来适应其必须携带的电流的容量。