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公开(公告)号：US08466503B2
公开(公告)日：2013-06-18
申请号：US12189298
申请日：2008-08-11
IPC分类号： H01L29/76
CPC分类号： H01L29/66477 , H01L21/26506 , H01L21/28052 , H01L21/28114 , H01L21/28518 , H01L29/1083 , H01L29/42376 , H01L29/66507 , H01L29/6659 , H01L29/66772 , H01L29/66795 , H01L29/785 , H01L29/78654
摘要： A semiconductor transistor with an expanded top portion of a gate and a method for forming the same. The semiconductor transistor with an expanded top portion of a gate includes (a) a semiconductor region which includes a channel region and first and second source/drain regions; the channel region is disposed between the first and second source/drain regions, (b) a gate dielectric region in direct physical contact with the channel region, and (c) a gate electrode region which includes a top portion and a bottom portion. The bottom portion is in direct physical contact with the gate dielectric region. A first width of the top portion is greater than a second width of the bottom portion. The gate electrode region is electrically insulated from the channel region by the gate dielectric region.
摘要翻译： 具有扩大的栅极顶部的半导体晶体管及其形成方法。 具有扩大的栅极顶部的半导体晶体管包括：（a）包括沟道区和第一和第二源极/漏极区的半导体区; 沟道区域设置在第一和第二源极/漏极区域之间，（b）与沟道区域直接物理接触的栅极电介质区域，以及（c）包括顶部和底部的栅电极区域。 底部部分与栅极电介质区域直接物理接触。 顶部的第一宽度大于底部的第二宽度。 栅电极区域通过栅极电介质区域与沟道区域电绝缘。
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公开(公告)号：US08354351B2
公开(公告)日：2013-01-15
申请号：US12610630
申请日：2009-11-02
IPC分类号： H01L21/00
CPC分类号： B23K26/0626 , B23K26/0608 , H01L21/26513 , H01L21/2686
摘要： A system for configuring and utilizing J electromagnetic radiation sources (J≧2) to serially irradiate a substrate. Each source has a different function of wavelength and angular distribution of emitted radiation. The substrate includes a base layer and I stacks (I≧2; J≦I) thereon. Pj denotes a same source-specific normally incident energy flux on each stack from source j. In each of I independent exposure steps, the I stacks are concurrently exposed to radiation from the J sources. Vi and Si respectively denote an actual and target energy flux transmitted into the substrate via stack i in exposure step i (i=1, . . . , I). t(i) and Pt(i) are computed such that: Vi is maximal through deployment of source t(i) as compared with deployment of any other source for i=1, . . . , I; and an error E being a function of |V1−S1|, |V2−S2|, . . . , |VI−SI| is about minimized with respect to Pi (i=1, . . . , I).
摘要翻译： 一种用于配置和利用J电磁辐射源（J≥2）以串行照射衬底的系统。 每个源具有不同的发射辐射的波长和角分布的功能。 衬底包括基层和I堆叠（I≥2; J＆lt; I; I）。 Pj表示来自源j的每个堆叠上相同的源特定的正常入射能量通量。 在I独立暴露步骤中，I堆叠同时暴露于来自J源的辐射。 Vi和Si分别表示在曝光步骤i（i = 1，...，I）中通过堆叠i传输到衬底中的实际和目标能量通量。 计算t（i）和Pt（i），使得：与部署i = 1的任何其他源相比，通过部署源t（i），Vi最大。 。 。 ， 一世; 并且误差E是| V1-S1 |，| V2-S2 |的函数。 。 。 ，| VI-SI | 相对于Pi（i = 1，...，I）被最小化。
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公开(公告)号：US07964465B2
公开(公告)日：2011-06-21
申请号：US12104475
申请日：2008-04-17
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L29/66795 , H01L29/785
摘要： A structure formation method. First, a structure is provided including (a) a fin region comprising (i) a first source/drain portion having a first surface and a third surface parallel to each other, not coplanar, and both exposed to a surrounding ambient, (ii) a second source/drain portion having a second surface and a fourth surface parallel to each other, not coplanar, and both exposed to the surrounding ambient, and (iii) a channel region disposed between the first and second source/drain portions, (b) a gate dielectric layer, and (c) a gate electrode region, wherein the gate dielectric layer (i) is sandwiched between, and (ii) electrically insulates the gate electrode region and the channel region. Next, a patterned covering layer is used to cover the first and second surfaces but not the third and fourth surfaces. Then, the first and second source/drain portions are etched at the third and fourth surfaces, respectively.
摘要翻译： 一种结构形成方法。 首先，提供一种结构，其包括（a）翅片区域，其包括：（i）第一源极/漏极部分，其具有彼此平行的第一表面和第三表面，不共面，并且暴露于周围环境;（ii） 第二源极/漏极部分，具有彼此平行的第二表面和第四表面，不共面，并暴露于周围环境;以及（iii）设置在第一和第二源极/漏极部分之间的沟道区域，（b ）栅介质层，和（c）栅电极区，其中所述栅介质层（i）夹在其间，和（ii）使所述栅电极区和所述沟道区电绝缘。 接下来，使用图案化覆盖层来覆盖第一表面和第二表面而不是第三表面和第四表面。 然后，分别在第三和第四表面处蚀刻第一和第二源极/漏极部分。
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公开(公告)号：US07790636B2
公开(公告)日：2010-09-07
申请号：US11427410
申请日：2006-06-29
CPC分类号： H01L21/268
摘要： A method for configuring J electromagnetic radiation sources (J≧2) to simultaneously irradiate a substrate. Each source has a different function of wavelength and angular distribution of emitted radiation. The substrate includes a base layer and I stacks (I≧2) thereon. Pj denotes a same source-specific normally incident energy flux on each stack from source j. For simultaneous exposure of the I stacks to radiation from the J sources, Pj is computed such that an error E being a function of |W1−S1|, |W2−S2, . . . , |WI−SI| is about minimized with respect to Pj=1, . . . , J). Wi and Si respectively denote an actual and target energy flux transmitted into the substrate via stack i (i=1, . . . , I). The stacks are exposed to the radiation from the sources characterized by the computed Pj (j=1, . . . , J).
摘要翻译： 一种用于配置J电磁辐射源（J≥2）以同时照射衬底的方法。 每个源具有不同的发射辐射的波长和角分布的功能。 基板包括基层和I堆叠（I≥2）。 Pj表示来自源j的每个堆叠上相同的源特定的正常入射能量通量。 为了将I堆叠同时暴露于来自J源的辐射，计算Pj，使得误差E是| W1-S1 |，| W2-S2的函数。 。 。 ，| WI-SI | 关于Pj = 1，关于最小化。 。 。 ，J）。 Wi和Si分别表示通过堆叠i（i = 1，...，I）传输到衬底中的实际和目标能量通量。 这些堆叠暴露于由所计算的Pj（j = 1，...，J）表征的源的辐射。
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公开(公告)号：US20090261380A1
公开(公告)日：2009-10-22
申请号：US12104513
申请日：2008-04-17
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7848
摘要： A semiconductor structure. The structure includes (a) a fin region having (i) a first source/drain portion having a first surface and a third surface, wherein the first and third surfaces are (A) parallel to each other and (B) not coplanar, (ii) a second source/drain portion having a second surface and a fourth surface, wherein the second and fourth surfaces are (A) parallel to each other and (B) not coplanar, and (iii) a channel region; (b) a gate dielectric layer; (c) a gate electrode region, wherein the gate dielectric layer (i) is sandwiched between, and (ii) electrically insulates the gate electrode region and the channel region; and (d) first second strain creating regions on the third and fourth surfaces, respectively, wherein the first and second strain creating regions comprise a strain creating material.
摘要翻译： 半导体结构。 该结构包括（a）翅片区域，其具有（i）具有第一表面和第三表面的第一源极/漏极部分，其中第一和第三表面是彼此平行的（A）和（B）不是共面的，（ ii）具有第二表面和第四表面的第二源极/漏极部分，其中第二和第四表面是彼此平行的（A）和（B）不共面的，（iii）沟道区域; （b）栅介质层; （c）栅极电极区域，其中所述栅极电介质层（i）夹在其间，和（ii）使所述栅电极区域和所述沟道区域电绝缘; 和（d）分别在第三和第四表面上的第一第二应变产生区域，其中第一和第二应变产生区域包括应变产生材料。
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公开(公告)号：US20080282208A1
公开(公告)日：2008-11-13
申请号：US12139632
申请日：2008-06-16
IPC分类号： G06F17/50
CPC分类号： G06F21/75
摘要： An article of manufacture, for example, a product or portion of a product produced by an IP design house which, when manufactured, causes random failures in a counterfeit integrated circuit. The article of manufacture (520) is a “genetic code” that comprises all of the necessary functional information needed to build an electronic circuit. This article of manufacture, when processed in a computer-aided design system and/or a fabrication facility, generates a functional apparatus such as an anti-counterfeiting circuit.
摘要翻译： 制造品，例如，由IP设计公司生产的产品或产品的一部分，其在制造时在假冒集成电路中引起随机故障。 制造品（520）是包括构建电子电路所需的所有必要功能信息的“遗传密码”。 本制造商在计算机辅助设计系统和/或制造设备中进行处理时，生成诸如防伪电路的功能装置。
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7.发明申请Structure for Designing an Integrated Circuit Having Anti-counterfeiting Measures 审中-公开设计具有防伪措施的集成电路的结构公开(公告)号：US20080282206A1
公开(公告)日：2008-11-13
申请号：US12139641
申请日：2008-06-16
IPC分类号： G06F17/50
CPC分类号： G06F21/445
摘要： A design structure for an anti-counterfeiting circuit that is incorporated into an authentic integrated circuit (IC) design, which induces a random failure in a counterfeited IC when the counterfeit IC is manufactured from a reverse-engineered authentic IC. The anti-counterfeiting circuit uses two signals of differing frequencies, which activate a disrupt signal when the two signals meet a predetermined failure criteria, for example, equivalent rising edges. The disrupt signal causes a signal gate or similar element within the counterfeited IC to fail, disrupt, or in some way change a designed behavior of the IC. The disrupt signal may be reset so that the failure will occur again when predetermined failure criteria are met. The authentic IC functions according to design because at least one of the elements in the anti-counterfeit circuit is a camouflage circuit, thus, in an authentic IC the anti-counterfeit circuit is not operatively coupled.
摘要翻译： 一种用于防伪电路的设计结构，其被并入真正的集成电路（IC）设计中，当假冒IC由反向工程认证IC制造时，其在假冒IC中引发随机故障。 防伪电路使用两个不同频率的信号，当两个信号满足预定的故障标准（例如等效的上升沿）时，该信号激活中断信号。 该扰乱信号导致伪造IC内的信号门或类似元件故障，中断或以某种方式改变IC的设计行为。 可以复位中断信号，以便在满足预定的故障标准时再次发生故障。 由于防伪电路中的至少一个元件是伪装电路，所以可信赖的IC功能根据设计，因此，在可靠的IC中，防伪电路不可操作地耦合。
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公开(公告)号：US20080217694A1
公开(公告)日：2008-09-11
申请号：US12124410
申请日：2008-05-21
IPC分类号： H01L29/423
CPC分类号： H01L29/785 , H01L29/66795
摘要： A spacer structure for FinFETs. The structure includes (a) a substrate, (b) a semiconductor fin region on top of the substrate, (c) a gate dielectric region on side walls of the semiconductor fin region, and (d) a gate electrode region on top and on side walls of the semiconductor fin region. The gate dielectric region (i) is sandwiched between and (ii) electrically insulates the gate electrode region and the semiconductor fin region. The structure further includes a first spacer region on a first side wall of the gate electrode region. A first side wall of the semiconductor fin region is exposed to a surrounding ambient. A top surface of the first spacer region is coplanar with a top surface of the gate electrode region.
摘要翻译： FinFET的间隔结构。 该结构包括（a）衬底，（b）在衬底的顶部上的半导体鳍片区域，（c）半导体鳍片区域的侧壁上的栅极电介质区域，以及（d）顶部和上部的栅电极区域 半导体鳍片区域的侧壁。 栅极电介质区域（i）夹在其间并且（ii）使栅电极区域和半导体鳍片区域电绝缘。 该结构还包括在栅电极区域的第一侧壁上的第一间隔区域。 半导体鳍片区域的第一侧壁暴露于周围环境。 第一间隔区域的顶表面与栅电极区域的顶表面共面。
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公开(公告)号：US06605981B2
公开(公告)日：2003-08-12
申请号：US09842544
申请日：2001-04-26
申请人： Andres Bryant , Peter Edwin Cottrell , John Joseph Ellis-Monaghan , Mark B. Ketchen , Edward Joseph Nowak
发明人： Andres Bryant , Peter Edwin Cottrell , John Joseph Ellis-Monaghan , Mark B. Ketchen , Edward Joseph Nowak
IPC分类号： G05F302
CPC分类号： G05F3/205 , H01L27/0218
摘要： An apparatus for biasing ultra-low voltage logic circuits is disclosed. An integrated circuit device includes multiple transistors and a global body bias circuit. The global body bias circuit includes a first transistor and second transistors connected in series between a power supply and a second power supply or ground. The gate and source of the first transistor are connected to the first power supply. The gate and source of the second transistor are connected to the second power supply. The drains and bodies of the first and second transistors are connected together to form an output connected to the bodies of the other transistors within the integrated circuit device.
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10.发明授权公开(公告)号：US06459106B2
公开(公告)日：2002-10-01
申请号：US09753521
申请日：2001-01-03
IPC分类号： H01L29768
CPC分类号： H01L21/84 , H01L29/78609 , H01L29/78612
摘要： Described is a dynamic threshold field effect transistor (DTFET) that includes a gate-to-body contact structure within the gate. By forming the gate-to-body contact structure that can reduce the gate-to-body contact resistance and increase the device packing density, the DTFET can be used in silicon on insulator (SOI) technologies and take full advantages of the DT-CMOS performance benefit.
摘要翻译： 描述了一种动态阈值场效应晶体管（DTFET），其包括栅极内的栅对体接触结构。 通过形成能够降低栅对体接触电阻并增加器件封装密度的栅对体接触结构，DTFET可用于绝缘体上硅（SOI）技术，并充分利用了DT-CMOS 性能优势。
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