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公开(公告)号：US09252241B2
公开(公告)日：2016-02-02
申请号：US14031100
申请日：2013-09-19
Inventor： Him Chan Oh , Chi Sun Hwang , Sang Hee Park
IPC: H01L29/66 , H01L29/786 , H01L29/45
CPC classification number: H01L29/78696 , H01L29/24 , H01L29/45 , H01L29/4908 , H01L29/66742 , H01L29/66969 , H01L29/7869
Abstract: Disclosed are a self-aligned thin film transistor capable of simultaneously improving an operation speed and stability and minimizing a size thereof by forming source and drain electrodes so as to be self-aligned, and a fabrication method thereof. The method of fabricating a thin film transistor according to an exemplary embodiment of the present disclosure includes: forming an active layer, a gate insulator, and a gate layer on a substrate; forming a photoresist layer pattern for defining a shape of a gate electrode on the gate layer; etching the gate layer, the gate insulator, and the active layer by using the photoresist layer pattern; depositing a source and drain layer on the etched substrate by a deposition method having directionality; and forming a gate electrode and self-aligned source electrode and drain electrode by removing the photoresist layer pattern.
Abstract translation: 本发明公开了一种自对准薄膜晶体管及其制造方法，其能够同时提高操作速度和稳定性，并且通过形成源极和漏极以自对准地使其尺寸最小化。 根据本公开的示例性实施例的制造薄膜晶体管的方法包括：在衬底上形成有源层，栅极绝缘体和栅极层; 形成用于限定所述栅极层上的栅电极的形状的光致抗蚀剂层图案; 通过使用光致抗蚀剂层图案蚀刻栅极层，栅极绝缘体和有源层; 通过具有方向性的沉积方法在蚀刻的衬底上沉积源极和漏极层; 以及通过去除光致抗蚀剂层图案形成栅电极和自对准源电极和漏电极。
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公开(公告)号：US20140145180A1
公开(公告)日：2014-05-29
申请号：US14031100
申请日：2013-09-19
Inventor： Him Chan Oh , Chi Sun Hwang , Sang Hee Park
IPC: H01L29/66 , H01L29/786
CPC classification number: H01L29/78696 , H01L29/24 , H01L29/45 , H01L29/4908 , H01L29/66742 , H01L29/66969 , H01L29/7869
Abstract: Disclosed are a self-aligned thin film transistor capable of simultaneously improving an operation speed and stability and minimizing a size thereof by forming source and drain electrodes so as to be self-aligned, and a fabrication method thereof. The method of fabricating a thin film transistor according to an exemplary embodiment of the present disclosure includes: forming an active layer, a gate insulator, and a gate layer on a substrate; forming a photoresist layer pattern for defining a shape of a gate electrode on the gate layer; etching the gate layer, the gate insulator, and the active layer by using the photoresist layer pattern; depositing a source and drain layer on the etched substrate by a deposition method having directionality; and forming a gate electrode and self-aligned source electrode and drain electrode by removing the photoresist layer pattern.
Abstract translation: 本发明公开了一种自对准薄膜晶体管及其制造方法，其能够同时提高操作速度和稳定性，并且通过形成源极和漏极以自对准地使其尺寸最小化。 根据本公开的示例性实施例的制造薄膜晶体管的方法包括：在衬底上形成有源层，栅极绝缘体和栅极层; 形成用于限定所述栅极层上的栅电极的形状的光致抗蚀剂层图案; 通过使用光致抗蚀剂层图案蚀刻栅极层，栅极绝缘体和有源层; 通过具有方向性的沉积方法在蚀刻的衬底上沉积源极和漏极层; 以及通过去除光致抗蚀剂层图案形成栅电极和自对准源电极和漏电极。
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公开(公告)号：US08716035B2
公开(公告)日：2014-05-06
申请号：US14022705
申请日：2013-09-10
Inventor： Sung Min Yoon , Chun Won Byun , Shin Hyuk Yang , Sang Hee Park , Soon Won Jung , Seung Youl Kang , Chi Sun Hwang , Byoung Gon Yu
IPC: H01L51/00
CPC classification number: H01L29/6684 , B82Y10/00 , G11C11/22 , H01L21/28291 , H01L27/1159 , H01L29/78391
Abstract: Provided are a nonvolatile memory cell and a method of manufacturing the same. The nonvolatile memory cell includes a memory transistor and a driver transistor. The memory transistor includes a semiconductor layer, a buffer layer, an organic ferroelectric layer, and a gate electrode, which are disposed on a substrate. The driver transistor includes the semiconductor layer, the buffer layer, a gate insulating layer, and the gate electrode, which are disposed on the substrate. The memory transistor and the driver transistor are disposed on the same substrate. The nonvolatile memory cell is transparent in a visible light region.
Abstract translation: 提供一种非易失性存储单元及其制造方法。 非易失性存储单元包括存储晶体管和驱动晶体管。 存储晶体管包括设置在基板上的半导体层，缓冲层，有机铁电层和栅极电极。 驱动晶体管包括设置在基板上的半导体层，缓冲层，栅极绝缘层和栅极电极。 存储晶体管和驱动晶体管设置在同一衬底上。 非易失性存储单元在可见光区域是透明的。
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公开(公告)号：US08710866B2
公开(公告)日：2014-04-29
申请号：US14050313
申请日：2013-10-09
Inventor： Sang Hee Park , Chi Sun Hwang , Sung Min Yoon , Him Chan Oh , Kee Chan Park , Tao Ren , Hong Kyun Leem , Min Woo Oh , Ji Sun Kim , Jae Eun Pi , Byeong Hoon Kim , Byoung Gon Yu
IPC: H03K19/20
CPC classification number: H03K3/012 , H03K19/094 , H03K19/20
Abstract: Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal.
Abstract translation: 公开了一种逆变器，NAND门和NOR门。 逆变器包括：上拉单元，由根据施加到栅极的电压向输出端子输出第一电源电压的第二薄膜晶体管构成; 根据施加到门的输入信号，将由接地电压输出到输出端的第五薄膜晶体管构成的下拉单元; 以及根据输入信号将第二电源电压或接地电压施加到第二薄膜晶体管的栅极的上拉驱动器。
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5.发明授权Self-aligned thin film transistor with doping barrier and method of manufacturing the same 有权具有掺杂势垒的自对准薄膜晶体管及其制造方法公开(公告)号：US09245978B2
公开(公告)日：2016-01-26
申请号：US13960352
申请日：2013-08-06
Inventor： Chi Sun Hwang , Sang Hee Park , Him Chan Oh
IPC: H01L27/12 , H01L29/66 , H01L29/786
CPC classification number: H01L29/66742 , H01L29/66969 , H01L29/78618 , H01L29/7869
Abstract: Disclosed are a self-aligned thin film transistor controlling a diffusion length of a doping material using a doping barrier in a thin film transistor having a self-aligned structure and a method of manufacturing the same. The self-aligned thin film transistor with a doping barrier includes: an active layer formed on a substrate and having a first doping region, a second doping region, and a channel region; a gate insulating film formed on the channel region; a gate electrode formed on the gate insulating film; a doping source film formed on the first doping region and the second doping region; and a doping barrier formed between the doping source film and the first doping region and between the doping source film and the second doping region.
Abstract translation: 公开了一种在具有自对准结构的薄膜晶体管中使用掺杂阻挡层控制掺杂材料的扩散长度的自对准薄膜晶体及其制造方法。 具有掺杂势垒的自对准薄膜晶体管包括：形成在衬底上并具有第一掺杂区，第二掺杂区和沟道区的有源层; 形成在沟道区上的栅极绝缘膜; 形成在栅极绝缘膜上的栅电极; 形成在所述第一掺杂区域和所述第二掺杂区域上的掺杂源膜; 以及在掺杂源膜和第一掺杂区之间以及在掺杂源膜和第二掺杂区之间形成的掺杂势垒。
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Patent Agency Ranking
公开(公告)号：US20130161732A1
公开(公告)日：2013-06-27
申请号：US13712428
申请日：2012-12-12
Inventor： Chi Sun HWANG , Sang Hee Park
IPC: H01L29/78
CPC classification number: H01L29/7827 , H01L29/41733 , H01L29/78642
Abstract: Disclosed is a vertical channel thin film transistor including a substrate; a drain electrode formed on the substrate; a spacer formed on the substrate while coming into contact with the drain electrode; a source electrode formed on the spacer; an active layer formed on an entire surface of the substrate including the drain electrode and the source electrode and configured to form a vertical channel; a gate insulating layer formed on the active layer; and a gate electrode formed on the gate insulating layer.
Abstract translation: 公开了一种包括衬底的垂直沟道薄膜晶体管; 形成在所述基板上的漏电极; 在与所述漏电极接触的同时在所述基板上形成的间隔物; 形成在间隔物上的源电极; 形成在包括所述漏电极和所述源电极的所述基板的整个表面上的有源层，并且被构造成形成垂直沟道; 形成在所述有源层上的栅极绝缘层; 以及形成在栅极绝缘层上的栅电极。
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公开(公告)号：US09099991B2
公开(公告)日：2015-08-04
申请号：US14049800
申请日：2013-10-09
Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE , Konkuk University Industrial Cooperation Corp
Inventor： Sang Hee Park , Chi Sun Hwang , Sung Min Yoon , Him Chan Oh , Kee Chan Park , Tao Ren , Hong Kyung Leem , Min Woo Oh , Ji Sun Kim , Jae Eun Pi , Byeong Hoon Kim , Byoung Gon Yu
IPC: H03K19/20 , H03K19/094 , H03K3/012
CPC classification number: H03K3/012 , H03K19/094 , H03K19/20
Abstract: Disclosed are an inverter, a NAND gate, and a NOR gate. The inverter includes: a pull-up unit constituted by a second thin film transistor outputting a first power voltage to an output terminal according to a voltage applied to a gate; a pull-down unit constituted by a fifth thin film transistor outputting a ground voltage to the output terminal according to an input signal applied to a gate; and a pull-up driver applying a second power voltage or the ground voltage to the gate of the second thin film transistor according to the input signal.
Abstract translation: 公开了一种逆变器，NAND门和NOR门。 逆变器包括：上拉单元，由根据施加到栅极的电压向输出端子输出第一电源电压的第二薄膜晶体管构成; 根据施加到门的输入信号，将由接地电压输出到输出端的第五薄膜晶体管构成的下拉单元; 以及根据输入信号将第二电源电压或接地电压施加到第二薄膜晶体管的栅极的上拉驱动器。
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公开(公告)号：US09299758B2
公开(公告)日：2016-03-29
申请号：US13960413
申请日：2013-08-06
Inventor： Sang Hee Park , Chi Sun Hwang
IPC: H01L27/32 , H01L51/52 , G02F1/1335
CPC classification number: H01L27/3267 , G02F1/133553 , G02F2001/133626 , H01L51/5271
Abstract: Disclosed is a dual display device having a vertical structure, in which a reflective display device and a self-emissive display device are formed on one substrate in a vertical structure so as to enable a reflective display or a self-emissive display according to a situation and provide a high resolution display. The dual display device having a vertical structure includes: a thin film transistor formed on a substrate; a white light emitting device formed on the thin film transistor: a reflection adjusting layer formed on the white light emitting device; and a color converting layer formed on the reflection adjusting layer.
Abstract translation: 公开了一种具有垂直结构的双显示装置，其中反射显示装置和自发光显示装置以垂直结构形成在一个基板上，以便能够根据情况进行反射显示或自发显示 并提供高分辨率显示。 具有垂直结构的双显示装置包括：形成在基板上的薄膜晶体管; 形成在所述薄膜晶体管上的白色发光器件，形成在所述白色发光器件上的反射调节层; 以及形成在反射调节层上的颜色转换层。
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9.发明授权公开(公告)号：US09025233B2
公开(公告)日：2015-05-05
申请号：US13677723
申请日：2012-11-15
Inventor： Hojun Ryu , Sang Hee Park
IPC: G09G5/10 , G02B26/00 , G02F1/157 , G02B5/20 , G09G5/00 , G09G3/20 , G09G3/22 , G09G3/34 , G09G3/32
CPC classification number: G09G5/10 , G02B5/201 , G02B26/001 , G02F1/157 , G02F2201/44 , G09G3/2003 , G09G3/22 , G09G3/3208 , G09G3/3466 , G09G3/3473 , G09G5/00 , G09G2300/023 , G09G2300/0452 , G09G2300/046
Abstract: Disclosed is a dual mode function pixel that operates either in a first mode or in a second mode according to the intensity of a projected light to have a high visibility regardless of the intensity of projected light. The dual mode function pixel includes: a first membrane on which a self-luminescent element is formed; one or more membranes formed to surround the first membrane; and a lower layer formed below the first membrane and the one or more membranes to be spaced apart from the first membrane and the one or more membranes. The dual mode function pixel is controlled such that the self-luminescent element is driven either to emit light in a first mode operation or to selectively reflect a projected light by utilizing an interference of light generated between the first to one or more membranes and the lower layer in a second mode operation.
Abstract translation: 公开了一种双模式功能像素，其可以根据投影光的强度在第一模式或第二模式中操作以具有高可见度，而与投射光的强度无关。 双模式功能像素包括：形成有自发光元件的第一膜; 形成为围绕第一膜的一个或多个膜; 以及形成在第一膜下面的下层和与第一膜和一个或多个膜间隔开的一个或多个膜。 控制双模式功能像素，使得自发光元件被驱动以在第一模式操作中发光或者通过利用在第一至一个或多个膜之间产生的光的干涉而选择性地反射投影光， 层在第二模式操作。
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公开(公告)号：US08841665B2
公开(公告)日：2014-09-23
申请号：US13849111
申请日：2013-03-22
Inventor： Sang Hee Park , Min Ki Ryu , Him Chan Oh , Chi Sun Hwang
IPC: H01L21/16 , H01L21/76 , H01L21/00 , H01L29/786 , H01L29/66
CPC classification number: H01L29/7869 , H01L29/66742
Abstract: Disclosed is a method for manufacturing an oxide thin film transistor, including: forming a gate electrode on a substrate on which a buffer layer is formed; forming a gate insulation layer on an entire surface of the substrate on which the gate electrode is formed; forming an oxide semiconductor layer on the gate insulation layer; forming a first etch stop layer on the oxide semiconductor layer; forming a second etch stop layer on the first etch stop layer by an atomic layer deposition method; patterning the first etch stop layer and the second etch stop layer, or forming a contact hole, through which a part of the oxide semiconductor layer is exposed, in the first etch stop layer and the second etch stop layer; forming a source electrode and a drain electrode on the first etch stop layer and the second etch stop layer; and forming a passivation layer on the entire surface of the substrate on which the source electrode and the drain electrode are formed.
Abstract translation: 公开了一种制造氧化物薄膜晶体管的方法，包括：在其上形成有缓冲层的基板上形成栅电极; 在其上形成有栅电极的基板的整个表面上形成栅极绝缘层; 在所述栅极绝缘层上形成氧化物半导体层; 在所述氧化物半导体层上形成第一蚀刻停止层; 通过原子层沉积法在第一蚀刻停止层上形成第二蚀刻停止层; 在第一蚀刻停止层和第二蚀刻停止层中形成第一蚀刻停止层和第二蚀刻停止层，或形成暴露氧化物半导体层的一部分的接触孔; 在所述第一蚀刻停止层和所述第二蚀刻停止层上形成源电极和漏电极; 以及在其上形成有源电极和漏电极的基板的整个表面上形成钝化层。
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