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1.发明申请公开(公告)号：US20200234635A1
公开(公告)日：2020-07-23
申请号：US16838629
申请日：2020-04-02
Inventor： Woo Joo LEE , Suk Ho LEE , Kyung Jin BYUN , Nak Woong EUM
IPC: G09G3/3208 , H05B45/00 , H05B45/37 , G09G3/20 , G06F3/14 , G06F1/3218
Abstract: Provided is a display device including a display panel, a power delivery network (PDN), an image controller, and a PDN controller. The display panel may include a plurality of sub-panels. The PDN may be controlled by a control signal, respectively deliver voltages determined by the control signal to the plurality of sub-panels, and generate state information for determining the control signal. The image controller may receive to store frame image data, determine a number of frames to be integrated according to a window size, and integrate the frame image data of frames in the determined number into one image to generate integrated image data. The PDN controller may generate the control signal and a size adjusting signal based on the state information and the integrated image data, provide the generated control signal to the PDN, and may provide the generated size adjusting signal to the image controller. The size adjusting signal may adjust the window size.
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公开(公告)号：US20170257632A1
公开(公告)日：2017-09-07
申请号：US15232542
申请日：2016-08-09
Inventor： Sukho LEE , Kyung Jin BYUN , Nak Woong EUM
IPC: H04N19/159 , H04N19/182 , H04N19/96 , H04N19/61 , H04N19/124 , H04N19/13 , H04N19/176 , H04N19/122
CPC classification number: H04N19/159 , H04N19/11 , H04N19/122 , H04N19/124 , H04N19/13 , H04N19/176 , H04N19/182 , H04N19/463 , H04N19/61 , H04N19/96
Abstract: Provided is an encoding method of an image encoding device including predicting an intra mode for coding blocks of a minimum size for intra prediction to generate an intra pixel; and using the intra mode of the coding blocks of the minimum size to restore an intra mode of coding blocks of a larger size.
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公开(公告)号：US20170222648A1
公开(公告)日：2017-08-03
申请号：US15414236
申请日：2017-01-24
Inventor： Woojoo LEE , Young-Su KWON , Kyung Jin BYUN , Jin Ho HAN , Nak Woong EUM
IPC: H03K19/00
CPC classification number: H03K19/0013 , G06F3/0202 , H01L27/1104 , H01L29/49 , H03K17/9638 , H03K19/00369 , H03K19/0944
Abstract: An Ultra Low Voltage (ULV) digital circuit includes a logic circuit comprising a plurality of logic gates and a plurality of buffered interconnects for connecting between the plurality of logic gates, a temperature sensor configured to detect a temperature of the logic circuit, and a voltage controller configured to control a driving voltage provided to the logic circuit in order to reduce a power consumption of the logic circuit based on the detected temperature. Each of the plurality of logic gates and buffered interconnects reduces a signal delay as a temperature increases.
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4.发明申请HIGH EFFICIENCY VIDEO CODING (HEVC) INTRA PREDICTION ENCODING APPARATUS AND METHOD 审中-公开高效率视频编码（HEVC）内部预测编码设备和方法公开(公告)号：US20150063452A1
公开(公告)日：2015-03-05
申请号：US14304405
申请日：2014-06-13
Inventor： Ig Kyun KIM , Kyung Jin BYUN , Nak Woong EUM
IPC: H04N19/593 , H04N19/61 , H04N19/186 , H04N19/124 , H04N19/96 , H04N19/182
CPC classification number: H04N19/11 , H04N19/147 , H04N19/176 , H04N19/186 , H04N19/593 , H04N19/96
Abstract: Disclosed is a residual signal inter-channel intra prediction encoding method between a residual signal of a luminance component of an image and a residual signal of a chrominance component thereof. It is possible to improve an intra prediction encoding performance when the inter-channel prediction is performed between residual signal of the luminance component and the chrominance component of HEVC, and derive a prediction coefficient for linear prediction at a high speed while the quadtree block structure of the HEVC is not changed. In addition, it is advantageous to avoid degradation in inter-channel prediction performance, which is caused when quadtree block structures of prediction units (PUs) of the luminance component and the chrominance component are different.
Abstract translation: 公开了一种在图像的亮度分量的残留信号和其色度分量的残留信号之间的残留信号的信道间帧内预测编码方法。 当在亮度分量的残留信号和HEVC的色度分量之间执行信道间预测时，可以提高帧内预测编码性能，并且导出用于高速线性预测的预测系数，而四叉树块结构 HEVC没有改变。 此外，有利的是避免在亮度分量和色度分量的预测单元（PU）的四叉树块结构不同时引起的信道间预测性能的劣化。
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5.发明申请公开(公告)号：US20180293935A1
公开(公告)日：2018-10-11
申请号：US15766464
申请日：2017-01-25
Inventor： Woo Joo LEE , Suk Ho LEE , Kyung Jin BYUN , Nak Woong EUM
IPC: G09G3/3208 , H05B33/08 , G06F1/32 , G06F3/14
Abstract: Provided is a display device including a display panel, a power delivery network (PDN), an image controller, and a PDN controller. The display panel may include a plurality of sub-panels. The PDN may be controlled by a control signal, respectively deliver voltages determined by the control signal to the plurality of sub-panels, and generate state information for determining the control signal. The image controller may receive to store frame image data, determine a number of frames to be integrated according to a window size, and integrate the frame image data of frames in the determined number into one image to generate integrated image data. The PDN controller may generate the control signal and a size adjusting signal based on the state information and the integrated image data, provide the generated control signal to the PDN, and may provide the generated size adjusting signal to the image controller. The size adjusting signal may adjust the window size.
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Patent Agency Ranking
公开(公告)号：US20170255554A1
公开(公告)日：2017-09-07
申请号：US15241902
申请日：2016-08-19
Inventor： Jin Ho HAN , Young-Su KWON , Kyung Jin BYUN , Nak Woong EUM
IPC: G06F12/0811 , G06F12/0842 , G06F12/0875 , G06F12/084
CPC classification number: G06F12/0811 , G06F12/084 , G06F12/0842 , G06F12/0875 , G06F2212/6042 , G06F2212/62
Abstract: Provided is a cache memory. The cache memory includes a first to Nth level-1 caches configured to correspond to first to Nth cores, respectively, a level-2 sharing cache configured to be shared by the first to Nth level-1 caches, and a coherence controller configured to receive an address from each of the first to Nth cores and allocate at least a partial area in an area of the level-2 sharing cache to one of the first to Nth level-1 caches based on the received address.
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公开(公告)号：US20170255520A1
公开(公告)日：2017-09-07
申请号：US15241808
申请日：2016-08-19
Inventor： Jin Ho HAN , Young-Su KWON , Kyoung Seon SHIN , Kyung Jin BYUN , Nak Woong EUM
IPC: G06F11/10 , G06F12/0895 , G06F12/0804
CPC classification number: G06F11/1076 , G06F12/0804 , G06F12/0808 , G06F12/0864 , G06F12/0895 , G06F12/0897 , G06F2212/1032
Abstract: Provided is an operating method of a cache memory device includes receiving an address from an external device, reading an entry corresponding to at least a portion of the received address among a plurality of entries that are included in the cache memory, performing error detection on additional information that is included in the read entry, and performing a recovery operation on the entry based on a result of error detection and the additional information. The entry includes the additional information and a cache line corresponding to the additional information, and the additional information includes a tag, valid bit, and dirty bit that correspond to the cache line.
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公开(公告)号：US20170262011A1
公开(公告)日：2017-09-14
申请号：US15432588
申请日：2017-02-14
Inventor： Young-Su KWON , Kyung Jin BYUN , Nak Woong EUM
CPC classification number: G06F11/1608 , G06F1/06 , G06F1/12 , G06F11/0724 , G06F11/1641 , G06F11/1675 , G06F11/1679
Abstract: Provided is a processor system including a first processor driven by a first driving voltage and a first driving clock, a second processor driven by a second driving voltage and a second driving clock and configured to perform an identical task to the first processor, and a defect detector configured to perform level synchronization or clock domain synchronization on a first output signal provided from the first processor and a second output signal provided from the second processor to compare the first and second output signals, wherein the first and second driving voltages are respectively provided from mutually independent power supply sources and the first and second driving clocks are respectively provided from mutually independent clock generators.
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公开(公告)号：US20170206102A1
公开(公告)日：2017-07-20
申请号：US15408210
申请日：2017-01-17
Inventor： Jae-Jin LEE , Hyeong Uk JANG , Kyung Jin BYUN , Nak Woong EUM
CPC classification number: G06F9/455 , G06F9/4451 , G06F17/30979 , G06F21/00 , G06F21/53 , G06F21/88
Abstract: An electronic device configured to perform forensic analysis on a target device includes a data extractor, an emulator, and a user data converter. The data extractor obtains, from the target device, a source file of at least one of applications installed on the target device. The data extractor obtains, from the target device, user data generated according to the least one of the applications being executed in the target device. The emulator emulates an execution of a target application installed based on the obtained source file. The user data converter converts the obtained user data having a data structure according to a database scheme of the target device into converted user data having a data structure according to a database scheme of the emulator. The emulator emulates the execution of the target application such that the target application operates using the converted user data.
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公开(公告)号：US20170192885A1
公开(公告)日：2017-07-06
申请号：US15222940
申请日：2016-07-28
Inventor： Jae-Jin LEE , Kyung Jin BYUN , Nak Woong EUM
IPC: G06F12/084 , G06F12/0875 , G06F9/30 , G06F12/0842
CPC classification number: G06F12/084 , G06F9/3017 , G06F12/0842 , G06F12/0875 , G06F17/5022 , G06F2212/452 , G06F2212/62 , G06F2217/68
Abstract: Provided is a multi-core simulation method including allocating, to a working memory, a shared translation block cache commonly used for a plurality of core models, reading a first target instruction to be performed in a first core model, generating a first translation block corresponding to the first target instruction and provided with an instruction set used in a host processor, performing the first translation block in the first core model after the first translation block is stored in the shared translation block cache, reading a second target instruction to be performed in a second core model, searching the shared translation block cache for a translation block including same content as that of the second target instruction, and performing the first translation block in the second core model, when the first target instruction includes same content as that of the second target instruction.
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