-
公开(公告)号：US20240104962A1
公开(公告)日：2024-03-28
申请号：US18340686
申请日：2023-06-23
Inventor： Tae Wook KANG , Sung Eun KIM , Kyung Jin BYUN , Kwang IL OH , Jae-Jin LEE
CPC classification number: G06V40/40 , G06V10/70 , G06V40/1306
Abstract: Disclosed are a fingerprint forgery detection device and a method of operating the same. The fingerprint forgery detection device includes a memory that stores a first feature signal including biological channel feature information of a user, a transmitter including at least one transmission electrode for transmitting a pulse signal to the user, a receiver including at least one reception electrode for receiving a biological channel response signal in response to the transmitted pulse signal, and a signal processor for processing the biological channel response signal to detect whether a fingerprint is forged, and at least one processor that controls the memory, the transmitter, and the receiver.
-
公开(公告)号：US20230289582A1
公开(公告)日：2023-09-14
申请号：US18084234
申请日：2022-12-19
Inventor： Young Hwan BAE , Jae-Jin LEE , Tae Wook KANG , Sung Eun KIM , Kyung Jin BYUN , Kwang IL OH , In San JEON
Abstract: A neuron circuit including a first internal circuit that receives a plurality of spike input signals, generates a first sum value by summing a plurality of synaptic weights corresponding to the plurality of spike input signals, and outputs a second sum value by adding a membrane potential value to the first sum value, a spike generating circuit that generates a spike output signal, a membrane potential generating circuit that generates the membrane potential value, a second internal circuit that counts a last spike time based on the spike output signal, and an online learning circuit that receives a last input time from the first internal circuit and performs LTP learning based on the last input time or receives the last spike time from the second internal circuit and performs LTD learning based on the last spike time.
-
公开(公告)号：US20200315438A1
公开(公告)日：2020-10-08
申请号：US16842497
申请日：2020-04-07
Inventor： Kwang IL OH , Tae Wook KANG , Sung Eun KIM , Hyuk KIM , Mi Jeong PARK , Hyung-IL PARK , Kyung Jin BYUN , Jae-Jin LEE , In Gi LIM
Abstract: A capsule endoscope image receiver includes a receiving electrode unit that receives first and second differential signals from a capsule endoscope image transmitter through a human body communication channel, an analog amplifying unit that receives the first and second differential signals and outputs first and second amplified differential signals, and a signal restoring unit that receives the first and second amplified differential signals and restores image information. The analog amplifying unit includes a first amplifier that outputs the first amplified differential signal, a second amplifier that outputs the second amplified differential signal, and an input impedance that is connected between a first inverting input terminal of the first amplifier and a second inverting input terminal of the second amplifier and obtains a gain of differential signal amplification in which a high frequency component of the first and second amplified differential signals is greater than a low frequency component.
-
公开(公告)号：US20170257632A1
公开(公告)日：2017-09-07
申请号：US15232542
申请日：2016-08-09
Inventor： Sukho LEE , Kyung Jin BYUN , Nak Woong EUM
IPC: H04N19/159 , H04N19/182 , H04N19/96 , H04N19/61 , H04N19/124 , H04N19/13 , H04N19/176 , H04N19/122
CPC classification number: H04N19/159 , H04N19/11 , H04N19/122 , H04N19/124 , H04N19/13 , H04N19/176 , H04N19/182 , H04N19/463 , H04N19/61 , H04N19/96
Abstract: Provided is an encoding method of an image encoding device including predicting an intra mode for coding blocks of a minimum size for intra prediction to generate an intra pixel; and using the intra mode of the coding blocks of the minimum size to restore an intra mode of coding blocks of a larger size.
-
公开(公告)号：US20170222648A1
公开(公告)日：2017-08-03
申请号：US15414236
申请日：2017-01-24
Inventor： Woojoo LEE , Young-Su KWON , Kyung Jin BYUN , Jin Ho HAN , Nak Woong EUM
IPC: H03K19/00
CPC classification number: H03K19/0013 , G06F3/0202 , H01L27/1104 , H01L29/49 , H03K17/9638 , H03K19/00369 , H03K19/0944
Abstract: An Ultra Low Voltage (ULV) digital circuit includes a logic circuit comprising a plurality of logic gates and a plurality of buffered interconnects for connecting between the plurality of logic gates, a temperature sensor configured to detect a temperature of the logic circuit, and a voltage controller configured to control a driving voltage provided to the logic circuit in order to reduce a power consumption of the logic circuit based on the detected temperature. Each of the plurality of logic gates and buffered interconnects reduces a signal delay as a temperature increases.
-
Patent Agency Ranking
公开(公告)号：US20150149836A1
公开(公告)日：2015-05-28
申请号：US14547301
申请日：2014-11-19
Inventor： Young Su KWON , Jin Ho HAN , Kyung Jin BYUN
IPC: G06F11/07
CPC classification number: G06F11/0772 , G06F11/0721 , G06F11/183
Abstract: A recoverable and fault-tolerant CPU core and a control method thereof are provided. The recoverable and fault-tolerant CPU core includes first, second, and third arithmetic logic circuits configured to perform a calculation requested by the same instruction, a first selector configured to compare calculation values output from the first, second, and third arithmetic logic circuits by the same instruction, determine as a normal state when two or more of the calculation values are the same, and if not, determine as a fault state, and a register file configured to record the calculation value having the same value, when determining as the normal state in the first selector.
Abstract translation: 提供了一种可恢复和容错的CPU内核及其控制方法。 可恢复和容错CPU核心包括被配置为执行由相同指令请求的计算的第一，第二和第三算术逻辑电路，第一选择器被配置为将从第一，第二和第三算术逻辑电路输出的计算值与 相同的指令，当两个或多个计算值相同时确定为正常状态，如果不是，则确定为故障状态，以及配置为记录具有相同值的计算值的寄存器文件，当确定为 第一选择器中的正常状态。
-
7.发明申请HIGH EFFICIENCY VIDEO CODING (HEVC) INTRA PREDICTION ENCODING APPARATUS AND METHOD 审中-公开高效率视频编码（HEVC）内部预测编码设备和方法公开(公告)号：US20150063452A1
公开(公告)日：2015-03-05
申请号：US14304405
申请日：2014-06-13
Inventor： Ig Kyun KIM , Kyung Jin BYUN , Nak Woong EUM
IPC: H04N19/593 , H04N19/61 , H04N19/186 , H04N19/124 , H04N19/96 , H04N19/182
CPC classification number: H04N19/11 , H04N19/147 , H04N19/176 , H04N19/186 , H04N19/593 , H04N19/96
Abstract: Disclosed is a residual signal inter-channel intra prediction encoding method between a residual signal of a luminance component of an image and a residual signal of a chrominance component thereof. It is possible to improve an intra prediction encoding performance when the inter-channel prediction is performed between residual signal of the luminance component and the chrominance component of HEVC, and derive a prediction coefficient for linear prediction at a high speed while the quadtree block structure of the HEVC is not changed. In addition, it is advantageous to avoid degradation in inter-channel prediction performance, which is caused when quadtree block structures of prediction units (PUs) of the luminance component and the chrominance component are different.
Abstract translation: 公开了一种在图像的亮度分量的残留信号和其色度分量的残留信号之间的残留信号的信道间帧内预测编码方法。 当在亮度分量的残留信号和HEVC的色度分量之间执行信道间预测时，可以提高帧内预测编码性能，并且导出用于高速线性预测的预测系数，而四叉树块结构 HEVC没有改变。 此外，有利的是避免在亮度分量和色度分量的预测单元（PU）的四叉树块结构不同时引起的信道间预测性能的劣化。
-
公开(公告)号：US20250123981A1
公开(公告)日：2025-04-17
申请号：US18912740
申请日：2024-10-11
Inventor： Kyuseung HAN , Hyuk KIM , Kyung Jin BYUN , Sukho LEE , Jae-Jin LEE
IPC: G06F13/36
Abstract: Provided is a communication method by which a transmitting device and a receiving device communicate through a request channel and a reply channel, the communication method including: outputting, by the transmitting device, a burden signal including data to the receiving device through the request channel; storing, by the receiving device, the data; providing, by the transmitting signal, a reply request signal indicating whether a reply is required; and performing, by the receiving device, a reply to the stored data through the reply channel according to the reply request signal.
-
公开(公告)号：US20230306247A1
公开(公告)日：2023-09-28
申请号：US18073830
申请日：2022-12-02
Inventor： In San JEON , Hyuk KIM , Jae-Jin LEE , Tae Wook KANG , Sung Eun KIM , Young Hwan BAE , Kyung Jin BYUN , Kwang IL OH
Abstract: Disclosed is a neuron circuit, which includes a first bias circuit that adds a bias current to an input current to generate a biased input current, a logarithm-based neuron calculation circuit that performs a logarithm calculation on an amount of current of the biased input current to generate an input logarithm value and generates a biased output voltage by performing a logarithm-based Hodgkin-Huxley model calculation based on the input logarithm value, and a second bias circuit that adds a bias voltage to the biased output voltage to generate an output voltage.
-
公开(公告)号：US20230140256A1
公开(公告)日：2023-05-04
申请号：US17965393
申请日：2022-10-13
Inventor： Sung Eun KIM , Tae Wook KANG , Hyuk KIM , Young Hwan BAE , Kyung Jin BYUN , Kwang IL OH , Jae-Jin LEE , In San JEON
Abstract: Disclosed is an electronic device that supports a neural network including a neuron array including neurons, a row address encoder that receives spike signals from neurons and outputs request signals in response to the received spike signals, and a row arbiter tree that receives request signals from the row address encoder and outputs response signals in response to the received request signals. The row arbiter tree includes a first arbiter that arbitrates first and second request signals among request signals, a first latch circuit that stores a state of the first arbiter, a second arbiter that arbitrates third and fourth request signals among request signals, a second latch circuit that stores a state of the second arbiter, and a third arbiter that delivers a response signal to the first and second arbiters based on information stored in the first and second latch circuits.
-
-
-
-
-
-
-
-
-
Search Results
41
records
(took 0.044 seconds)
