公开(公告)号：US20150143045A1

公开(公告)日：2015-05-21

申请号：US14253466

申请日：2014-04-15

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jin Ho HAN ,  Young Su KWON ,  Kyoung Seon SHIN

IPC: G06F12/08

CPC classification number: G06F12/0897 ,  G06F12/0862 ,  G06F2212/1021 ,  G06F2212/6022

Abstract: Provided are a cache control apparatus and method for reducing a miss penalty. The cache control apparatus includes a first level cache configured to store data in a memory, a second level cache connected to the first level cache, and configured to be accessed by a processor when the first level cache fails to call data according to a data request instruction, a prefetch buffer connected to the first and second level caches, and configured to temporarily store data transferred from the first and second level caches to a core, and a write buffer connected to the first level cache, and configured to receive address information and data of the first level cache.

Abstract translation: 提供了一种用于减少未命中罚款的高速缓存控制装置和方法。 高速缓存控制装置包括被配置为将数据存储在存储器中的第一级高速缓存，连接到第一级高速缓存的第二级高速缓存，并且被配置为当第一级高速缓存不能根据数据请求调用数据时被处理器访问 指令，连接到第一和第二级高速缓存的预取缓冲器，并且被配置为将从第一和第二级别高速缓存传送的数据临时存储到核心，以及连接到第一级高速缓存的写缓冲器，并且被配置为接收地址信息和 第一级缓存的数据。

公开(公告)号：US20150309862A1

公开(公告)日：2015-10-29

申请号：US14690843

申请日：2015-04-20

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jin Ho HAN ,  Young Su KWON

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F3/0673 ,  G06F3/0619 ,  G06F3/064 ,  G06F11/1064

Abstract: The cache control device having the fault-tolerant function includes a cache memory configured to store first data with respect to a specific address read from a main memory, and generate and store a first parity bit corresponding to the first data, a shadow cache memory configured to store second data with respect to the specific address, and generate and store a second parity bit corresponding to the second data, and a fault detector configured to perform a parity check operation on the data of the specific address and the parity bit stored in at least one of the cache memory and the shadow cache memory when receiving a data read request with respect to the specific address from a processor, and transmit the data stored in a non-erroneous memory to the processor according to a result of the parity check operation.

Abstract translation: 具有容错功能的高速缓存控制装置包括高速缓存存储器，被配置为存储关于从主存储器读取的特定地址的第一数据，并且生成并存储对应于第一数据的第一奇偶校验位， 存储关于特定地址的第二数据，并且生成并存储与第二数据相对应的第二奇偶校验位;以及故障检测器，被配置为对存储在其中的特定地址和奇偶校验位的数据执行奇偶校验操作 当从处理器接收关于特定地址的数据读取请求时，缓存存储器和影子高速缓存存储器中的至少一个，并且根据奇偶校验操作的结果将存储在非错误存储器中的数据发送到处理器 。

公开(公告)号：US20150212849A1

公开(公告)日：2015-07-30

申请号：US14602857

申请日：2015-01-22

Applicant: Electronics and Telecommunications Research Institute

Inventor： Jae Jin LEE ,  Young Su KWON

IPC: G06F9/46

CPC classification number: G06F9/461 ,  G06F9/455

Abstract: Provided are an apparatus and method for multicore emulation based on dynamic context switching. The apparatus for multicore emulation based on dynamic context switching includes a multicore emulation managing unit configured to transmit a signal for requesting determination of a core to be emulated among a plurality of cores, and a context switching managing unit configured to receive the signal for requesting determination of a core to be emulated from the multicore emulation managing unit, determine an ID of a core to be emulated according to the received signal, and executing emulation on a core corresponding to the determined core ID.

Abstract translation: 提供了一种基于动态上下文切换的多核仿真的装置和方法。 基于动态上下文切换的多核心仿真装置包括：多核仿真管理单元，被配置为发送用于请求确定要在多个核心中仿真的核心的信号;以及上下文切换管理单元，被配置为接收用于请求确定的信号 要从多核仿真管理单元仿真的核心，根据接收到的信号确定要仿真的核心的ID，以及对与所确定的核心ID相对应的核心执行仿真。

公开(公告)号：US20150149836A1

公开(公告)日：2015-05-28

申请号：US14547301

申请日：2014-11-19

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Young Su KWON ,  Jin Ho HAN ,  Kyung Jin BYUN

IPC: G06F11/07

CPC classification number: G06F11/0772 ,  G06F11/0721 ,  G06F11/183

Abstract: A recoverable and fault-tolerant CPU core and a control method thereof are provided. The recoverable and fault-tolerant CPU core includes first, second, and third arithmetic logic circuits configured to perform a calculation requested by the same instruction, a first selector configured to compare calculation values output from the first, second, and third arithmetic logic circuits by the same instruction, determine as a normal state when two or more of the calculation values are the same, and if not, determine as a fault state, and a register file configured to record the calculation value having the same value, when determining as the normal state in the first selector.

Abstract translation: 提供了一种可恢复和容错的CPU内核及其控制方法。 可恢复和容错CPU核心包括被配置为执行由相同指令请求的计算的第一，第二和第三算术逻辑电路，第一选择器被配置为将从第一，第二和第三算术逻辑电路输出的计算值与 相同的指令，当两个或多个计算值相同时确定为正常状态，如果不是，则确定为故障状态，以及配置为记录具有相同值的计算值的寄存器文件，当确定为 第一选择器中的正常状态。

公开(公告)号：US20140025894A1

公开(公告)日：2014-01-23

申请号：US13945049

申请日：2013-07-18

Applicant: Electronics and Telecommunications Research Institute

Inventor： Young Su KWON

IPC: G06F12/08

CPC classification number: G06F12/0875 ,  G06F9/3808 ,  G06F9/3861 ,  Y02D10/13

Abstract: A processor using a branch instruction execution cache and a method of operating the same are disclosed. The processor according to an example embodiment of the present invention includes a fetch unit, a branch prediction unit, an instruction queue, a decoding unit and an execution unit operating in a pipeline manner, and includes a branch instruction execution cache that stores address and decode information of a transferred instruction output from the decoding unit, and provides the stored address and at least some of pieces of the decode information to the execution unit in order to overcome branch misprediction when the execution unit determines the branch misprediction. Therefore, with the processor according to an example embodiment of the present invention, overhead of pipeline initialization can be minimized to prevent performance degradation of the processor and reduce power consumption of the processor.

Abstract translation: 公开了一种使用分支指令执行缓存的处理器及其操作方法。 根据本发明的示例性实施例的处理器包括以流水线方式操作的取指单元，分支预测单元，指令队列，解码单元和执行单元，并且包括存储地址和解码的分支指令执行高速缓存 从解码单元输出的传送指令的信息，并将存储的地址和解码信息的至少一部分提供给执行单元，以便在执行单元确定分支错误预测时克服分支错误预测。 因此，利用根据本发明的示例性实施例的处理器，可以最小化流水线初始化的开销，以防止处理器的性能下降并降低处理器的功耗。

公开(公告)号：US20150143049A1

公开(公告)日：2015-05-21

申请号：US14253349

申请日：2014-04-15

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jin Ho HAN ,  Young Su KWON ,  Kyoung Seon SHIN

IPC: G06F12/08

CPC classification number: G06F12/0875 ,  G06F12/0831 ,  G06F12/0833

Abstract: Provided is a cache control apparatus and method that, when a plurality of processors read a program from the same memory in a chip, maintain coherency of data and an instruction generated by a cache memory. The cache control apparatus includes a coherency controller client configured to include an MESI register, which is included in an instruction cache, and stores at least one of a modified state, an exclusive state, a shared state, and an invalid state for each line of the instruction cache, and a coherency interface connected to the coherency controller and configured to transmit and receive broadcast address information, read or write information, and hit or miss information of another cache to and from the instruction cache.

Abstract translation: 提供了一种缓存控制装置和方法，当多个处理器从芯片中的相同存储器读取程序时，保持数据的一致性和由高速缓存存储器生成的指令。 高速缓存控制装置包括：一致性控制器客户端，被配置为包括MESI寄存器，该MESI寄存器包括在指令高速缓存中，并且存储针对每行的修改状态，独占状态，共享状态和无效状态中的至少一个 指令高速缓存以及连接到一致性控制器并被配置为发送和接收广播地址信息，读取或写入信息以及将指向或从指令高速缓冲存储器中的另一个高速缓存的信息命中或丢失的一致性接口。

公开(公告)号：US20150006935A1

公开(公告)日：2015-01-01

申请号：US14300942

申请日：2014-06-10

Applicant: Electronics and Telecommunications Research Institute

Inventor： Jin Ho HAN ,  Young Su KWON ,  Kyoung Seon SHIN ,  Kyung Jin BYUN ,  Nak Woong EUM

IPC: G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/3206 ,  G06F12/0864 ,  G06F12/0895 ,  G06F2212/1028 ,  Y02D10/13 ,  Y02D10/14

Abstract: Disclosed are a processor capable of reducing power consumption of a cache by controlling power mode of the cache and a method for the same. A processor may comprise a processor core; a cache storing instructions to be executed in the processor core; and a cache management part controlling the cache based on a processor operation mode indicating a state of the processor core determined according to algorithm executed in the processor core. Thus, power consumption of cache may be reduced, and degradation of processor core performance may be prevented by controlling power mode of cache considering an operation mode of the processor.

Abstract translation: 公开了一种能够通过控制高速缓存的功率模式来降低高速缓存的功耗的处理器及其方法。 处理器可以包括处理器核心; 存储要在处理器核心中执行的指令的高速缓存; 以及高速缓存管理部，其基于指示根据在所述处理器核心中执行的算法确定的所述处理器核心的状态的处理器操作模式来控制所述高速缓存。 因此，可以降低高速缓存的功率消耗，并且可以通过考虑处理器的操作模式来控制高速缓存的功率模式来防止处理器核心性能的劣化。