公开(公告)号：US06893799B2

公开(公告)日：2005-05-17

申请号：US10248976

申请日：2003-03-06

申请人： David Danovitch ,  Stephen Kilpatrick

发明人： David Danovitch ,  Stephen Kilpatrick

IPC分类号： G03C5/00 ,  H01L21/288 ,  H01L21/60 ,  H01L21/66 ,  H01L21/68 ,  H01L23/488

CPC分类号： H01L21/6835 ,  H01L21/2885 ,  H01L22/14 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/056 ,  H01L2224/11003 ,  H01L2224/1147 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method to effectively deposit multi-component solders while remaining compatible with electroplating solder bumping process. A flip-chip solder bump is formed by using electroplated solder bump technology with the addition of wettable layer of metal or solder. The remainder of the required solder volume is deposited by Injection Molded Solder (IMS) technology. This method will accommodate certain metals, as well as trace amounts of alloying, that would be difficult or impossible to electroplate. The method also allows for electrical test between deposition of the wettable layer of solder and the bulk solder, providing the advantages of a more planar surface for probe contact, with very consistent height, less solder pick-up by the test probe and elimination of the post-probe solder reflow step.

摘要翻译： 一种有效沉积多组分焊料同时保持与电镀焊料焊接过程兼容的方法。 通过使用电镀焊料凸块技术，添加金属或焊料的可湿性层，形成倒装焊料凸块。 剩余的所需焊料体积通过注射成型焊料（IMS）技术沉积。 这种方法将适应某些金属，以及痕量的合金化，这将是难以或不可能的电镀。 该方法还允许在可润湿层的焊料沉积和块状焊料之间进行电气测试，提供用于探针接触的更平坦的表面的优点，具有非常一致的高度，较少的测试探针的焊接和消除 后探头回流焊步骤。

公开(公告)号：US20100276813A1

公开(公告)日：2010-11-04

申请号：US12839214

申请日：2010-07-19

申请人： Luc Belanger ,  David Danovitch ,  John U. Knickerbocker

发明人： Luc Belanger ,  David Danovitch ,  John U. Knickerbocker

IPC分类号： H01L23/488 ,  B23K31/02 ,  B23K1/20

CPC分类号： H01L24/11 ,  H01L25/0657 ,  H01L2224/13099 ,  H01L2224/48091 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2224/0401

摘要： A method of implementing an injection molded soldering process for three-dimensional structures, particularly, such as directed to three-dimensional semiconductor chip stacking. Also provide is an arrangement for implementing the injection molded soldering (IMS) process. Pursuant to an embodiment of the invention, the joining of the semiconductor chip layers with a substrate is implemented, rather than by means of currently known wire bond stacking, through the intermediary of columns of solder material formed by the IMS process, thereby providing electrical advantages imparted by the flip chip interconnect structures. In this connection, various diversely dimensioned solder column interconnects allow for simple and dependable connections to a substrate by a plurality of superimposed layers or stacked arrays of semiconductor components, such as semiconductor chips. In accordance with a further aspect, it is possible to derive a unique design for an IMS mold structure, which contains cavities for forming the columnar fill of solder, and which also incorporates further cavities acting as cutouts for dies or the positioning of other electronic packages or modules.

摘要翻译： 一种实现用于三维结构的注射成型焊接工艺的方法，特别是诸如针对三维半导体芯片堆叠的方法。 还提供了用于实现注射成型焊接（IMS）工艺的布置。 根据本发明的实施例，通过由IMS工艺形成的焊料柱的中间层，实现了半导体芯片层与基板的接合，而不是通过目前已知的引线键合堆叠，从而提供电气优点 由倒装芯片互连结构赋予。 在这方面，各种不同尺寸的焊料柱互连允许通过多个叠加层或诸如半导体芯片的半导体部件的堆叠阵列对衬底进行简单且可靠的连接。 根据另一方面，可以为IMS模具结构导出独特的设计，该模具结构包含用于形成焊料的柱状填充物的空腔，并且还包括用作模具的切口或其他电子封装的定位的另外的空腔 或模块。

公开(公告)号：US20070178625A1

公开(公告)日：2007-08-02

申请号：US11307291

申请日：2006-01-31

申请人： David Danovitch ,  Mukta Farooq ,  Michael Gaynes

发明人： David Danovitch ,  Mukta Farooq ,  Michael Gaynes

IPC分类号： H01L21/00

CPC分类号： H01L21/6835 ,  H01L21/4853 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/742 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2224/05599

摘要： Composite interconnect structure forming methods using injection molded solder are disclosed. The methods provide a mold having at least one opening formed therein with each opening including a member of a material dissimilar to a solder to be used to fill the opening, and then fill the remainder of each opening with solder to form the composite interconnect structure. The resulting composite interconnect structure can be leveraged to achieve a much larger variety of composite structures than exhibited by the prior art. For example, the material may be chosen to be more electrically conductive than the solder portion, more electromigration-resistant than the solder portion and/or more fatigue-resistant than the solder portion. In one embodiment, the composite interconnect structure can include an optical structure, or plastic or ceramic material. The optical structure provides radiation propagation and/or amplification between waveguides in the substrate and device, and the plastic material provides fatigue-resistance.

摘要翻译： 公开了使用注射成型焊料的复合互连结构形成方法。 该方法提供了一种具有形成在其中的至少一个开口的模具，每个开口包括与用于填充开口的焊料不同的材料的构件，然后用焊料填充每个开口的剩余部分以形成复合互连结构。 可以利用所得到的复合互连结构来实现比现有技术表现出的更大的复合结构。 例如，材料可以被选择为比焊料部分更具导电性，比焊料部分更具有电迁移性和/或比焊料部分更耐疲劳性。 在一个实施例中，复合互连结构可以包括光学结构，或塑料或陶瓷材料。 该光学结构在衬底和器件中的波导之间提供辐射传播和/或放大，并且塑料材料提供耐疲劳性。

公开(公告)号：US20120326290A1

公开(公告)日：2012-12-27

申请号：US13604341

申请日：2012-09-05

申请人： Paul S. Andry ,  Russell A. Budd ,  Bing Dang ,  David Danovitch ,  Benjamin V. Fasano ,  Paul Fortier ,  Luc Guerin ,  Frank R. Libsch ,  Sylvain Ouimet ,  Chrirag S. Patel

发明人： Paul S. Andry ,  Russell A. Budd ,  Bing Dang ,  David Danovitch ,  Benjamin V. Fasano ,  Paul Fortier ,  Luc Guerin ,  Frank R. Libsch ,  Sylvain Ouimet ,  Chrirag S. Patel

IPC分类号： H01L23/34 ,  H01L21/50

CPC分类号： H01L27/1446 ,  G02B6/4204 ,  G02B6/4249 ,  G02B6/4257 ,  G02B6/428 ,  G02B6/4292 ,  H01L23/367 ,  H01L25/16 ,  H01L27/14625 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01S5/005 ,  H01S5/0224 ,  H01S5/02248 ,  H01S5/02276 ,  H01S5/02284 ,  H01S5/02407 ,  H01S5/02476 ,  H01S5/183 ,  H01S5/423 ,  H01L2924/014 ,  H01L2924/00

摘要： An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board.

摘要翻译： 公开了一种用于制造的光电（OE）封装或系统和方法，其包括具有布线的硅层。 硅层具有允许光通过的光通孔。 光耦合层结合到硅层，并且光耦合层包括多个微透镜，用于聚焦和/或准直光穿过光通孔。 多个OE元件耦合到硅层并与布线电连通。 至少一个OE元件被定位成与用于接收光的光通孔光学对准。 载体介于电互连元件之间。 载体位于硅层的布线和电路板之间，并且载体电连接到连接到硅层的布线的第一互连元件和连接到电路板的第二互连元件。

公开(公告)号：US06819566B1

公开(公告)日：2004-11-16

申请号：US10605752

申请日：2003-10-23

申请人： David Danovitch ,  Eric Duchesne

发明人： David Danovitch ,  Eric Duchesne

IPC分类号： H05K720

CPC分类号： H01L23/3128 ,  H01L23/36 ,  H01L23/552 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/0401

摘要： In a microelectronic chip package for which grounding and thermal dissipation is desired, a cover is provided having an opening which is aligned with a contact on the substrate connected to ground potential. The cover is connected to the electronic device and the ground contact. This invention provides for a method and electronic package to overcome the difficulties encountered when attempting to simultaneously attach a cover to two different surfaces with two different adhesives.

摘要翻译： 在需要接地和散热的微电子芯片封装中，提供具有与连接到地电势的基板上的触点对准的开口的盖。 盖子连接到电子设备和接地触点。 本发明提供了一种方法和电子封装，以克服当试图用两种不同的粘合剂将盖子同时附接到两个不同的表面时遇到的困难。

公开(公告)号：US07952205B2

公开(公告)日：2011-05-31

申请号：US12839214

申请日：2010-07-19

申请人： Luc Belanger ,  David Danovitch ,  John U. Knickerbocker

发明人： Luc Belanger ,  David Danovitch ,  John U. Knickerbocker

IPC分类号： H01L29/40

CPC分类号： H01L24/11 ,  H01L25/0657 ,  H01L2224/13099 ,  H01L2224/48091 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2224/0401

摘要： A method of implementing an injection molded soldering process for three-dimensional structures, particularly, such as directed to three-dimensional semiconductor chip stacking. Also provide is an arrangement for implementing the injection molded soldering (IMS) process. Pursuant to an embodiment of the invention, the joining of the semiconductor chip layers with a substrate is implemented, rather than by means of currently known wire bond stacking, through the intermediary of columns of solder material formed by the IMS process, thereby providing electrical advantages imparted by the flip chip interconnect structures. In this connection, various diversely dimensioned solder column interconnects allow for simple and dependable connections to a substrate by a plurality of superimposed layers or stacked arrays of semiconductor components, such as semiconductor chips. In accordance with a further aspect, it is possible to derive a unique design for an IMS mold structure, which contains cavities for forming the columnar fill of solder, and which also incorporates further cavities acting as cutouts for dies or the positioning of other electronic packages or modules.

摘要翻译： 一种实现用于三维结构的注射成型焊接工艺的方法，特别是诸如针对三维半导体芯片堆叠的方法。 还提供了用于实现注射成型焊接（IMS）工艺的布置。 根据本发明的实施例，通过由IMS工艺形成的焊料柱的中间层，实现了半导体芯片层与基板的接合，而不是通过目前已知的引线键合堆叠，从而提供电气优点 由倒装芯片互连结构赋予。 在这方面，各种不同尺寸的焊料柱互连允许通过多个叠加层或诸如半导体芯片的半导体部件的堆叠阵列对衬底进行简单且可靠的连接。 根据另一方面，可以为IMS模具结构导出独特的设计，该模具结构包含用于形成焊料的柱状填充物的空腔，并且还包括用作模具的切口或其他电子封装的定位的另外的空腔 或模块。

公开(公告)号：US20110044369A1

公开(公告)日：2011-02-24

申请号：US12544696

申请日：2009-08-20

申请人： Paul S. Andry ,  Russell A. Budd ,  Bing Dang ,  David Danovitch ,  Benjamin V. Fasano ,  Paul Fortier ,  Luc Guerin ,  Frank R. Libsch ,  Sylvain Ouimet ,  Chirag S. Patel

发明人： Paul S. Andry ,  Russell A. Budd ,  Bing Dang ,  David Danovitch ,  Benjamin V. Fasano ,  Paul Fortier ,  Luc Guerin ,  Frank R. Libsch ,  Sylvain Ouimet ,  Chirag S. Patel

IPC分类号： H01S5/18 ,  H01L31/0232 ,  H01L23/34 ,  H01L21/50

CPC分类号： H01L27/1446 ,  G02B6/4204 ,  G02B6/4249 ,  G02B6/4257 ,  G02B6/428 ,  G02B6/4292 ,  H01L23/367 ,  H01L25/16 ,  H01L27/14625 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01S5/005 ,  H01S5/0224 ,  H01S5/02248 ,  H01S5/02276 ,  H01S5/02284 ,  H01S5/02407 ,  H01S5/02476 ,  H01S5/183 ,  H01S5/423 ,  H01L2924/014 ,  H01L2924/00

摘要： An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board.

摘要翻译： 公开了一种用于制造的光电（OE）封装或系统和方法，其包括具有布线的硅层。 硅层具有允许光通过的光通孔。 光耦合层结合到硅层，并且光耦合层包括多个微透镜，用于聚焦和/或准直光穿过光通孔。 多个OE元件耦合到硅层并与布线电连通。 至少一个OE元件被定位成与用于接收光的光通孔光学对准。 载体介于电互连元件之间。 载体位于硅层的布线和电路板之间，并且载体电连接到连接到硅层的布线的第一互连元件和连接到电路板的第二互连元件。

公开(公告)号：US07820483B2

公开(公告)日：2010-10-26

申请号：US11670543

申请日：2007-02-02

申请人： Luc Belanger ,  David Danovitch ,  John U. Knickerbocker

发明人： Luc Belanger ,  David Danovitch ,  John U. Knickerbocker

IPC分类号： H01L21/00

CPC分类号： H01L24/11 ,  H01L25/0657 ,  H01L2224/13099 ,  H01L2224/48091 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2224/0401

摘要： A method of implementing an injection molded soldering process for three-dimensional structures, particularly, such as directed to three-dimensional semiconductor chip stacking. Also provide is an arrangement for implementing the injection molded soldering (IMS) process. Pursuant to an embodiment of the invention, the joining of the semiconductor chip layers with a substrate is implemented, rather than by means of currently known wire bond stacking, through the intermediary of columns of solder material formed by the IMS process, thereby providing electrical advantages imparted by the flip chip interconnect structures. In this connection, various diversely dimensioned solder column interconnects allow for simple and dependable connections to a substrate by a plurality of superimposed layers or stacked arrays of semiconductor components, such as semiconductor chips. In accordance with a further aspect, it is possible to derive a unique design for an IMS mold structure, which contains cavities for forming the columnar fill of solder, and which also incorporates further cavities acting as cutouts for dies or the positioning of other electronic packages or modules.

摘要翻译： 一种实现用于三维结构的注射成型焊接工艺的方法，特别是诸如针对三维半导体芯片堆叠的方法。 还提供了用于实现注射成型焊接（IMS）工艺的布置。 根据本发明的实施例，通过由IMS工艺形成的焊料柱的中间层，实现了半导体芯片层与基板的接合，而不是通过目前已知的引线键合堆叠，从而提供电气优点 由倒装芯片互连结构赋予。 在这方面，各种不同尺寸的焊料柱互连允许通过多个叠加层或诸如半导体芯片的半导体部件的堆叠阵列对衬底进行简单且可靠的连接。 根据另一方面，可以为IMS模具结构导出独特的设计，该模具结构包含用于形成焊料的柱状填充物的空腔，并且还包括用作模具的切口或其他电子封装的定位的另外的空腔 或模块。

公开(公告)号：US06924171B2

公开(公告)日：2005-08-02

申请号：US09782494

申请日：2001-02-13

申请人： Stephen L. Buchwalter ,  David Danovitch ,  Fuad Elias Doany ,  Claudius Feger ,  Peter A. Gruber ,  Revathi Iyengar ,  Nancy C. LaBianca

发明人： Stephen L. Buchwalter ,  David Danovitch ,  Fuad Elias Doany ,  Claudius Feger ,  Peter A. Gruber ,  Revathi Iyengar ,  Nancy C. LaBianca

IPC分类号： H01L21/56 ,  H01L21/60 ,  H01L23/29 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L24/27 ,  H01L21/563 ,  H01L23/295 ,  H01L24/11 ,  H01L24/29 ,  H01L24/94 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/274 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83191 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/19041 ,  H01L2924/01083 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2224/05599

摘要： Methods for fabricating microelectronic interconnection structures as well as the structures formed by the methods are disclosed which improve the manufacturing throughput for assembling flip chip semiconductor devices. The use of a bilayer of polymeric materials applied on the wafer prior to dicing eliminates the need for dispensing and curing underfill for each semiconductor at the package level, thereby improving manufacturing throughput and reducing cost.

摘要翻译： 公开了制造微电子互连结构的方法以及通过这些方法形成的结构，其提高了组装倒装芯片半导体器件的制造吞吐量。 在切割之前使用在晶片上施加的聚合物材料的双层，消除了在封装级别为每个半导体分配和固化底部填充物的需要，从而提高制造产量并降低成本。

公开(公告)号：US08559474B2

公开(公告)日：2013-10-15

申请号：US13604341

申请日：2012-09-05

申请人： Paul S. Andry ,  Russell A. Budd ,  Bing Dang ,  David Danovitch ,  Benjamin V. Fasano ,  Paul Fortier ,  Luc Guerin ,  Frank F. Libsch ,  Sylvain Ouimet ,  Chrirag S. Patel

发明人： Paul S. Andry ,  Russell A. Budd ,  Bing Dang ,  David Danovitch ,  Benjamin V. Fasano ,  Paul Fortier ,  Luc Guerin ,  Frank F. Libsch ,  Sylvain Ouimet ,  Chrirag S. Patel

IPC分类号： H01S5/024 ,  H01S5/18 ,  H01L23/28 ,  H01L23/18

CPC分类号： H01L27/1446 ,  G02B6/4204 ,  G02B6/4249 ,  G02B6/4257 ,  G02B6/428 ,  G02B6/4292 ,  H01L23/367 ,  H01L25/16 ,  H01L27/14625 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01S5/005 ,  H01S5/0224 ,  H01S5/02248 ,  H01S5/02276 ,  H01S5/02284 ,  H01S5/02407 ,  H01S5/02476 ,  H01S5/183 ,  H01S5/423 ,  H01L2924/014 ,  H01L2924/00

摘要： An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board.

摘要翻译： 公开了一种用于制造的光电（OE）封装或系统和方法，其包括具有布线的硅层。 硅层具有允许光通过的光通孔。 光耦合层结合到硅层，并且光耦合层包括多个微透镜，用于聚焦和/或准直光穿过光通孔。 多个OE元件耦合到硅层并与布线电连通。 至少一个OE元件被定位成与用于接收光的光通孔光学对准。 载体介于电互连元件之间。 载体位于硅层的布线和电路板之间，并且载体电连接到连接到硅层的布线的第一互连元件和连接到电路板的第二互连元件。