公开(公告)号：US4920510A

公开(公告)日：1990-04-24

申请号：US63258

申请日：1987-06-17

申请人： Daniel Senderowicz ,  Guido Torelli ,  Germano Nicollini

发明人： Daniel Senderowicz ,  Guido Torelli ,  Germano Nicollini

IPC分类号： H03H15/00 ,  H03H17/02

CPC分类号： H03H17/02

摘要： The sampled-data band-pass filter device is based on the phenomemon of aliasing, and allows the substantially unattenuated passage of the components of an input signal at a frequency included within an interval comprised between a first frequency (f.sub.sL) and a second frequency (f.sub.sH), arranged around a third frequency (f.sub.sO), while it substantially attenuates the components of the input signal at frequencies outside said interval, and furthermore automatically performs the shift to low-frequency, around a fourth frequency (f.sub.O), of the components of the input signal which have passed without attenuation. According to the invention, the device comprises, as filter element, a sampled-data band-pass filter which employs, as sampling frequency, a fifth frequency (f.sub.s) equal to a whole submultiple of a sixth frequency (nf.sub.s) equal to the sum of the third frequency (f.sub.sO) and the fourth frequency (f.sub.O), having, as lower and upper cutoff frequencies, respectively the difference between the sixth frequency and the second frequency (nf.sub.s -f.sub.sH) and the difference between the sixth frequency and the first frequency (nf.sub.s -f.sub.sL).

摘要翻译： 采样数据带通滤波器装置基于混叠的特征，并且允许以包括在第一频率（fsL）和第二频率（fsL）之间的间隔内的频率的输入信号的分量的基本上未衰减的通过 fsH），其大致在第三频率（fs0）周围的频率衰减输入信号的分量，并且还自动地执行向组件的第四频率（f0）附近的低频移位 通过没有衰减的输入信号。 根据本发明，该装置包括作为滤波器元件的采样数据带通滤波器，采样数据带通滤波器采用等于等于总和的第六频率（nfs）的整数倍的第五频率（fs）作为采样频率 具有分别为第六频率和第二频率（nfs-fsH）之间的差和第六频率与第一频率之间的差的第三频率（fs0）和第四频率（f0）分别为下限和上限截止频率 频率（nfs-fsL）。

公开(公告)号：US06650173B1

公开(公告)日：2003-11-18

申请号：US09714852

申请日：2000-11-15

申请人： Osama Khouri ,  Rino Micheloni ,  Andrea Sacco ,  Guido Torelli

发明人： Osama Khouri ,  Rino Micheloni ,  Andrea Sacco ,  Guido Torelli

IPC分类号： G05F110

CPC分类号： G11C29/021 ,  G11C5/147 ,  G11C11/56 ,  G11C16/30 ,  G11C29/028 ,  G11C2029/5004

摘要： The voltage generator comprises a negative feedback loop including a programmable voltage divider having a feedback node. The voltage divider comprises a programmable resistor disposed between the output of the voltage generator and the feedback node and having variable resistance. The programmable resistor includes a fixed resistor and a plurality of additional resistors arranged in series with each other and defining a plurality of intermediate nodes. The additional resistors may be selectively connected by means of switches disposed between the output of the voltage generator and a respective intermediate node so as to define an output voltage V0 programmable on the basis of command signals supplied to the switches.

摘要翻译： 电压发生器包括负反馈回路，其包括具有反馈节点的可编程分压器。 分压器包括设置在电压发生器的输出端和反馈节点之间并具有可变电阻的可编程电阻器。 可编程电阻器包括固定电阻器和彼此串联布置并且限定多个中间节点的多个附加电阻器。 附加电阻器可以通过设置在电压发生器的输出端和各个中间节点之间的开关选择性地连接，以便根据提供给开关的命令信号来定义可编程的输出电压V0。

公开(公告)号：USRE38166E1

公开(公告)日：2003-07-01

申请号：US09410164

申请日：1999-09-30

申请人： Cristiano Calligaro ,  Vincenzo Daniele ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Nicola Telecco ,  Guido Torelli

发明人： Cristiano Calligaro ,  Vincenzo Daniele ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Nicola Telecco ,  Guido Torelli

IPC分类号： G11C1156

CPC分类号： G11C11/5621 ,  G11C11/5642 ,  G11C2211/5632

摘要： A sensing circuit for serial dichotomic sensing of multiple-level memory cells which can take one programming level among a plurality of m=2n (n>=2) different programming levels, comprises biasing means for biasing a memory cell to be sensed in a predetermined condition, so that the memory cell sinks a cell current with a value belonging to a plurality of m distinct cell current values, each cell current value corresponding to one of the programming levels, a current comparator for comparing the cell current with a reference current generated by a variable reference current generator, and a successive approximation register supplied with an output signal of the current comparator and controlling the variable reference current generator. The variable reference current generator comprises an offset current generator permanently coupled to the current comparator, and m−2 distinct current generators, independently activatable by the successive approximation register, each one generating a current equal to a respective one of the plurality of cell current values.

摘要翻译： 用于在多个m = 2n（n> = 2）不同编程级别中可以采用一个编程级的多级存储器单元的串行二分感测的感测电路包括偏置装置，用于以预定的方式偏置待感测的存储器单元 条件，使得存储器单元以属于多个m个不同的单元电流值的值吸收单元电流，每个单元电流值对应于一个编程电平，用于将单元电流与产生的参考电流进行比较的电流比较器 通过可变参考电流发生器和逐次逼近寄存器来提供电流比较器的输出信号并控制可变参考电流发生器。 可变参考电流发生器包括永久地耦合到电流比较器的偏移电流发生器和由逐次逼近寄存器独立激活的m-2个不同的电流发生器，每个电流发生器产生等于多个电池电流值中的相应一个的电流 。

公开(公告)号：US06288594B1

公开(公告)日：2001-09-11

申请号：US09674395

申请日：2000-10-30

申请人： Alessandro Manstretta ,  Andrea Pierin ,  Guido Torelli

发明人： Alessandro Manstretta ,  Andrea Pierin ,  Guido Torelli

IPC分类号： H03K1762

CPC分类号： G11C5/143

摘要： A monolithically integrated selector for electrically programmable memory cell devices can be switched at an output terminal (OUT) between a high voltage (HV) and a low voltage (LV). It comprises a leg (N2, N1) of fast ground discharge (GND) from the output terminal, a discharge control leg (P1, N3, N4) driving the selector switching through a phase generator (PHG).

摘要翻译： 用于电可编程存储单元器件的单片集成选择器可以在高电压（HV）和低电压（LV）之间的输出端（OUT）处切换。 它包括来自输出端子的快速放电（GND）的脚（N2，N1），驱动选择器切换通过相位发生器（PHG）的放电控制支路（P1，N3，N4）。

公开(公告)号：US4994730A

公开(公告)日：1991-02-19

申请号：US448498

申请日：1989-12-11

申请人： Domenico Rossi ,  Ermes Viani ,  Guido Torelli ,  Franco Maloberti ,  Carla Vacchi

发明人： Domenico Rossi ,  Ermes Viani ,  Guido Torelli ,  Franco Maloberti ,  Carla Vacchi

IPC分类号： G05F3/24 ,  G05F3/26

CPC分类号： G05F3/262

摘要： A current source circuit capable of generating two currents of opposite polarities. In order to generate the two currents, the circuit comprises a current source stage including a current mirror and feeding a first output current and an inverter stage connected to the source stage and generating a second output current with opposite polarity with respect to the first. The inverter stage comprises a current mirror and a variable current source defining a control electrode. In order to eliminate the differences in the amplitude of the output currents, the inverter stage comprises a memory element connected to the control electrode so as to store an electrode controlling signal. Switch elements are furthermore interposed between the first output and the second output so as to short-circuit them during the trimming step so that the two output currents are equal to one another while the memory element memorizes the control signal. This signal remains stored during the normal operation of the circuit.

公开(公告)号：US4631485A

公开(公告)日：1986-12-23

申请号：US687739

申请日：1984-12-28

申请人： Guido Torelli ,  Vincenzo Daniele

发明人： Guido Torelli ,  Vincenzo Daniele

IPC分类号： H03D1/22 ,  H03D1/06

CPC分类号： H03D1/2245

摘要： Two circuits carry out the beating of a modulated signal, with first and second signals, respectively, each having substantially the same frequency as the carrier of the modulated signal but phased-shifted relative to one another by 90.degree.. A commutator controlled by a control circuit alternately selects the signals resulting from the beating. The selection is responsive to the amplitudes of the signals in order to avoid losses of information due to amplitude peaks under a prefixed threshold which may be caused by frequency differences between the signals which are beat.

摘要翻译： 两个电路执行调制信号的跳动，第一和第二信号分别具有与调制信号的载波基本相同的频率，但相对于彼此相位相差90°。 由控制电路控制的换向器交替地选择由跳动产生的信号。 该选择响应于信号的振幅，以便避免由于可能由拍频信号之间的频率差引起的前缀阈值下的振幅峰值引起的信息损失。

公开(公告)号：US4587441A

公开(公告)日：1986-05-06

申请号：US541728

申请日：1983-10-13

申请人： Guido Torelli ,  Daniele Devecchi

发明人： Guido Torelli ,  Daniele Devecchi

IPC分类号： H03K19/017 ,  H03K19/0185 ,  H03K19/0944 ,  H03K3/353 ,  H03K3/017 ,  H03K5/05 ,  H03K5/156

CPC分类号： H03K19/01714 ,  H03K19/018507 ,  H03K19/09445

摘要： An interface circuit with MOS-type transistors for timing signal generators with two non-overlapping phases made up of two identical twin circuits, each having a final stage of the type including two transistors connected in series between the two terminals of a supply voltage generator and a bootstrap capacitor. Each of the two twin circuits includes a logic NOR circuit and a logic AND circuit which control, respectively, the charging and discharging of the capacitor through a suitable switching circuit connected to both terminals thereof. In each circuit, a memory circuit element is connected to the logic circuits. The memory circuit element is sensitive to the output signals of both twin circuits and enables the charging and discharging of the bootstrap capacitor at successive, logically produced time intervals which occur between the pulses of the output signals of both twin circuits.

摘要翻译： 一种具有用于定时信号发生器的MOS型晶体管的接口电路，具有由两个相同的双电路组成的两个非重叠相位，每个两个电路具有串联连接在电源电压发生器的两个端子之间的两个晶体管的类型的最终级， 自举电容器。 两个双电路中的每一个包括逻辑NOR电路和逻辑与电路，其分别通过连接到其两个端子的合适的开关电路来控制电容器的充电和放电。 在每个电路中，存储电路元件连接到逻辑电路。 存储电路元件对两个双电路的输出信号敏感，并且能够在两个双电路的输出信号的脉冲之间产生的逻辑上产生的时间间隔上进行自举电容器的充电和放电。

公开(公告)号：US4580063A

公开(公告)日：1986-04-01

申请号：US445858

申请日：1982-12-01

申请人： Guido Torelli ,  Giovanni Salomone

发明人： Guido Torelli ,  Giovanni Salomone

IPC分类号： H03K19/0944 ,  H03K5/08 ,  H03K17/0812 ,  H03K17/687 ,  H03K19/003 ,  H02H9/04 ,  H03K3/353 ,  H03K17/16

CPC分类号： H03K17/08122 ,  H03K19/00315 ,  H03K5/08

摘要： A pair of IGFETs connected in cascade across a d-c power supply form a source/drain junction constituting the output terminal of a self-biasing amplifier to which binary-coded bipolar signals are transmitted by way of a voltage divider effectively inserted between an input terminal and the afore-mentioned junction, a tap of that voltage divider being connected to the gate of a first of these IGFETs whose source is tied to one of the two supply terminals; the drain and the gate of the second IGFET are tied to the opposite supply terminal. A protective diode lies between the input terminal and the supply terminal connected to the source of the first IGFET so as to be reverse-biased by the voltage divider in a quiescent state and to break down in the presence of an abnormally high input voltage of a given polarity (positive in the specific instance described). An ancillary IGFET connected between the input terminal and the opposite supply terminal has its gate biased at a potential so chosen that this IGFET conducts in the presence of an input voltage of the other (negative) polarity approaching the forward-conduction threshold of the protective diode so as to prevent that threshold from being reached. The voltage divider may terminate at a source/drain junction of another pair of cascaded IGFETs that are identical with the IGFETs of the first pair and are connected in parallel therewith across the supply, the gate of the first IGFET of this other pair being tied to the last-mentioned source/drain junction which is also connected to the gate of the ancillary IGFET so as to bias same to the potential of the input and output terminals in the quiescent state in which the voltage divider is not traversed by any current.

摘要翻译： 跨直流电源串联连接的一对IGFET形成构成自偏置放大器的输出端的源极/漏极结，其中二进制编码的双极性信号通过分压器有效地传输到输入端子和 上述结点，该分压器的抽头连接到源极连接到两个电源端子之一的这些IGFET中的第一个的栅极; 第二个IGFET的漏极和栅极连接到相对的电源端子。 保护二极管位于输入端和连接到第一IGFET的源极的电源端之间，以便在静止状态下被分压器反向偏置，并且在存在异常高的输入电压 给定的极性（在所描述的具体实例中为正）。 连接在输入端子和相对电源端子之间的辅助IGFET的栅极偏置为一个电位，以便在存在接近保护二极管的正向导通阈值的另一（负）极性的输入电压的情况下，该IGFET导通 以防止达到该阈值。 分压器可以终止于与第一对的IGFET相同的另一对级联IGFET的源极/漏极结，并且跨越电源并联连接，该另一对的第一IGFET的栅极被连接到 最后提到的源极/漏极结也连接到辅助IGFET的栅极，以便将偏置相同于静态状态下的输入和输出端子的电位，其中分压器不被任何电流穿过。

公开(公告)号：US20100284212A1

公开(公告)日：2010-11-11

申请号：US12780580

申请日：2010-05-14

申请人： Ferdinando Bedeschi ,  Claudio Resta ,  Enzo Michele Donze ,  Roberto Gastaldi ,  Alessandro Cabrini ,  Guido Torelli

发明人： Ferdinando Bedeschi ,  Claudio Resta ,  Enzo Michele Donze ,  Roberto Gastaldi ,  Alessandro Cabrini ,  Guido Torelli

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0064 ,  G11C2013/0076 ,  G11C2013/0092

摘要： A method for programming multilevel PCM cells envisages: forming an amorphous region of amorphous phase change material in a storage element of a PCM cell by applying one or more reset pulse; and forming a conductive path of crystalline phase change material through the amorphous region by applying one or more set pulse, a size of the conductive path defining a programmed state of the PCM cell and an output electrical quantity associated thereto, and being controlled by the value of the reset pulse and set pulse. The step of forming an amorphous region envisages adaptively and iteratively determining, during the programming operations, a value of the reset pulse optimized for electrical and/or physical properties of the PCM cell, and in particular determining a minimum amplitude value of the reset pulse, which allows programming a desired programmed state and a desired value of the output electrical quantity.

摘要翻译： 用于编程多电平PCM单元的方法设想：通过施加一个或多个复位脉冲，在PCM单元的存储元件中形成非晶相变材料的非晶区域; 以及通过施加一个或多个设定脉冲，形成所述PCM单元的编程状态的导电路径的大小和与其相关联的输出电量，并通过所述值来控制所述晶体相变材料的导电路径通过所述非晶区域 的复位脉冲和设定脉冲。 形成非晶区域的步骤设想在编程操作期间自适应地和迭代地确定针对PCM单元的电气和/或物理特性优化的复位脉冲的值，特别是确定复位脉冲的最小振幅值， 这允许编程期望的编程状态和输出电量的期望值。

公开(公告)号：US07203087B2

公开(公告)日：2007-04-10

申请号：US11018550

申请日：2004-12-20

申请人： Claudio Resta ,  Ferdinando Bedeschi ,  Guido Torelli

发明人： Claudio Resta ,  Ferdinando Bedeschi ,  Guido Torelli

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C7/12 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004

摘要： A memory device having a reading configuration and including a plurality of memory cells, arranged in rows and columns, memory cells arranged on the same column having respective first terminals connected to a same bit line and memory cells arranged on the same row having respective second terminals selectively connectable to a same word line; a supply line providing a supply voltage; a column addressing circuit and a row addressing circuit for respectively addressing a bit line and a word line corresponding to a memory cell selected for reading in the reading configuration. The column addressing circuit is configured to bias the addressed bit line corresponding to the selected memory cell substantially at the supply voltage in the reading configuration. A row driving circuit biases the addressed word line corresponding to the selected memory cell at a non-zero word line read voltage, so that a predetermined cell voltage, lower than a phase change voltage, is applied between the first terminal and the second terminal of the selected memory cell in the reading configuration.

摘要翻译： 一种存储器件，具有读取配置，并且包括排列成行和列的多个存储器单元，布置在同一列上的存储器单元具有连接到相同位线的相应第一端子和布置在同一行上的存储器单元，该存储单元具有相应的第二端子 可选择性地连接到相同的字线; 提供电源电压的电源线; 列寻址电路和行寻址电路，用于分别寻址与读取配置中读取的存储单元对应的位线和字线。 列寻址电路被配置为在读取配置中基本上以电源电压偏置对应于所选存储单元的寻址位线。 行驱动电路以非零字线读取电压偏置对应于所选存储单元的寻址字线，使得在第一端和第二端之间施加低于相变电压的预定电池电压 读取配置中选定的存储单元。