-
公开(公告)号：US11955946B2
公开(公告)日：2024-04-09
申请号：US17221920
申请日：2021-04-05
CPC分类号： H03H7/12 , H03F3/19 , H03H7/0115 , H03H7/0161 , H03H9/6403 , H03H2007/006 , H03H2015/005
摘要： A tunable passband filter including a signal input port for receiving an input radio frequency (RF) signal, a signal output port for transmitting a filtered output RF signal, a first high-pass section having a first tunable microelectromechanical system (MEMS) switch array to receive the input RF signal from the signal input port, a second high-pass section having a second tunable MEMS switch array to transmit the output RF signal to the signal output port, and a low pass section operatively coupled between the first high-pass section and the second high-pass section, and having each of a first tunable MEMS bridge array, a second tunable MEMS bridge array, and a high impedance line. The tunable passband filter is configured to filter the input RF signal to yield the filtered output RF signal.
-
公开(公告)号：US20200321943A1
公开(公告)日：2020-10-08
申请号：US16838250
申请日：2020-04-02
发明人： Bartholomeus Jacobus Thijssen , Eric Antonius Maria Klumperink , Philip Eugene Quinlan , Bram Nauta
摘要： Systems and methods for analog finite impulse response (FIR) filters are provided. In certain embodiments, a receiver includes a cascade of a mixer, an analog FIR filter, and an analog-to-digital converter (ADC). By including the analog FIR filter along the signal path between the mixer and the ADC, design constraints of the ADC are relaxed. For example, the ADC can operate with relaxed specifications with respect to resolution and/or dynamic range when the analog FIR filter is included. The analog FIR filter can include a controllable transconductance circuit that delivers an integration current to a capacitor over an integration period, with the analog FIR filter's coefficients used to change the transconductance setting of the controllable transconductance circuit to different values over the integration period.
-
公开(公告)号：US10200014B2
公开(公告)日：2019-02-05
申请号：US15205170
申请日：2016-07-08
摘要： There is provided a communication receiver comprising: an input for receiving a radio frequency, RF, input signal; and at least one finite impulse response, FIR, discrete time filter, DTF. The at least one FIR DTF comprises: an input circuit comprising an input port for sampling the RF input signal at a sampling frequency that is comparable to the input RF input signal; and N parallel branches, each branch having a set of input unit sampling capacitances, where each unit sampling capacitance is independently selectively coupleable to an output summing node. The input circuit is configured to convert an equivalent input impedance of the at least one FIR DTF around the sampling frequency to a real impedance.
-
公开(公告)号：US10193532B2
公开(公告)日：2019-01-29
申请号：US15310666
申请日：2015-06-10
发明人： Jaeyoung Choi
摘要： According to one aspect of the invention, there is provided a method of operating a finite impulse response filter comprising an input; an output; and a plurality of storage elements, each coupled to the input via a sample switch and to the output via a transfer switch, the method comprising: during charging of the plurality of storage elements, applying a sample clock signal to each of the sample switches that achieves an operation mode where up to every one of the sample switches is simultaneously closed to connect all of the plurality of storage elements to the input; and during averaging of the plurality of storage elements, applying a transfer clock signal to each of the transfer switches to close one or more of the transfer switches to connect the storage elements, having charge stored therein, to the output.
-
公开(公告)号：US10056881B2
公开(公告)日：2018-08-21
申请号：US15443443
申请日：2017-02-27
CPC分类号： H03H19/004 , H03H15/00 , H03H15/023
摘要： A charge sharing filter includes a rotating capacitor, and a plurality of elementary filters, each elementary filter comprising: an elementary switch coupled between a first node of the respective elementary filter and a second node of the respective elementary filter; and a history capacitor coupled to the first node of the respective elementary filter, wherein the second nodes of the plurality of elementary filters are interconnected with the rotating capacitor in one interconnecting node.
-
公开(公告)号：US09923549B2
公开(公告)日：2018-03-20
申请号：US14849524
申请日：2015-09-09
申请人： Raytheon Company
摘要： There is provided a finite impulse response (FIR) filter for filtering an input voltage signal to generate an output current signal, the FIR filter including a plurality of sample and hold (SH) circuits configured to simultaneously receive the input voltage signal, to sample the input voltage signal at successive sample times according to a sample clock, and to generate a plurality of sampled voltage signals, and a plurality of programmable analog multipliers coupled to the plurality of SH circuits and configured to multiply the plurality of sampled voltage signals by a plurality of binary multiplication factors to generate the output current signal.
-
公开(公告)号：US09667288B1
公开(公告)日：2017-05-30
申请号：US14965535
申请日：2015-12-10
发明人： Swaroop Venkatesh , Vijay Ahirwar
CPC分类号： H04B1/1036 , H03H11/04 , H03H17/025 , H03H17/0294 , H03H17/04 , H03H2011/0488 , H03H2015/007 , H04B1/001 , H04B1/0475 , H04B1/1027 , H04B1/109 , H04B1/525 , H04B15/02 , H04B15/06 , H04B2001/1063 , H04B2215/064
摘要： The present disclosure includes systems and techniques relating to time-varying notch filter. In one implementation, an apparatus includes a time-variant notch filter and a controller. The time-variant notch filter includes a notch depth and a notch bandwidth centered on a notch frequency. At least one of the notch depth or the notch bandwidth is based on a coefficient of the notch filter. The controller is configured to estimate a power of a packet being received and compare the estimated power of the packet to a predetermined threshold. The controller is also configured to set, conditioned on determining that the estimated power of the packet is greater than the predetermined threshold, a value of the coefficient to a first value such that the packet bypasses the time-variant notch filter.
-
公开(公告)号：US20160294363A1
公开(公告)日：2016-10-06
申请号：US14879975
申请日：2015-10-09
申请人： ANALOG DEVICES, INC.
发明人： Eric G. Nestler
CPC分类号： H03H11/0405 , H03H15/00
摘要： A signal processing device has a first discrete time analog signal processing section, which has an input, an output, a plurality of charge storage elements, and plurality of switch elements coupling the charge storage elements. The device has a controller coupled to the first signal processing section configured to couple different subsets of the charge elements of the first signal processing section in successive operating phases to apply a signal processing function to an analog signal presented at the input of the first signal processing section and provide a result of the applying of the signal processing function as an analog signal to the output of first signal processing section. The signal processing function of the first signal processing section comprises a combination of a filtering function operating at a first sampling rate and one or more modulation functions operating at corresponding modulation rates lower than the first sampling rate.
-
公开(公告)号：US09318999B2
公开(公告)日：2016-04-19
申请号：US14368770
申请日：2013-01-22
发明人： Yohei Morishita
IPC分类号： H03D7/16 , H04B1/26 , H03D7/00 , H03D7/12 , H03D7/18 , G11C19/00 , G11C27/02 , H03H19/00 , H04B7/08 , H04L25/08 , H03H15/00 , H03D7/14
CPC分类号： H03D7/00 , G11C19/00 , G11C27/024 , H03D7/125 , H03D7/1441 , H03D7/18 , H03D2200/0062 , H03D2200/0068 , H03H15/00 , H03H19/004 , H04B7/0885 , H04L25/08
摘要： The sampling mixer circuit comprises: a clock generating circuit that outputs four-phase control signals the periods of which are in accordance with the carrier frequency of an input signal and the phases of which are different from one another; a voltage-to-current converting circuit that converts a voltage signal based on the input signal to a current signal; four-system charge sharing circuits in which the current signal as converted is input to a plurality of capacitors in accordance with the different phases based on the four-phase control signals and in which charges are exchanged among the plurality of capacitors; and a phase-to-phase capacitor that is selectively connected, on the basis of the four-phase control signals, to the respective ones of nodes, which are other than the input nodes of the current signal, in the four-system charge sharing circuits.
摘要翻译： 采样混频器电路包括：时钟发生电路，其输出其周期与输入信号的载波频率和相位彼此不同的四相控制信号; 电压 - 电流转换电路，其将基于所述输入信号的电压信号转换为电流信号; 四变系统电荷共享电路，其中根据四相控制信号将转换的电流信号输入到多个电容器，并且其中电荷在多个电容器之间交换; 以及基于四相控制信号在四系统电荷共享中被选择性地连接到不同于当前信号的输入节点的各个节点的相电容器 电路。
-
公开(公告)号：US08223756B2
公开(公告)日：2012-07-17
申请号：US11829163
申请日：2007-07-27
申请人： Yuji Ito , Masaya Oda , Shinichi Kuranari
发明人： Yuji Ito , Masaya Oda , Shinichi Kuranari
CPC分类号： H04L63/0227 , H04L63/101
摘要： A filter-information transmitting/receiving unit transmits path information with the filter information when the filter information is set by a filter setting unit, and receives the path information when the filter information is set in other network device. A filter-combining determining unit determines whether redundant filter information with the other network device is to be combined or deleted, based on the filter information and the path information. A filter control unit issues a filter-setting request or a filter release request based on a result of determination by the filter-combining determining unit.
摘要翻译： 当滤波器信息由滤波器设置单元设置时，滤波器信息发送/接收单元发送具有滤波器信息的路径信息，并且当在其他网络设备中设置滤波器信息时接收路径信息。 滤波器组合确定单元基于过滤器信息和路径信息来确定是否组合或删除与其他网络设备的冗余过滤器信息。 滤波器控制单元基于滤波器组合确定单元的确定结果发出滤波器设置请求或滤波器释放请求。
-
-
-
-
-
-
-
-
-
搜索结果
510 条记录 (耗时 0.03 秒)
