公开(公告)号：US06452841B1

公开(公告)日：2002-09-17

申请号：US09721470

申请日：2000-11-22

申请人： Richard Ferrant

发明人： Richard Ferrant

IPC分类号： G11C1156

CPC分类号： G11C7/106 ,  G11C7/06 ,  G11C7/103 ,  G11C7/1051 ,  G11C7/1069 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/412 ,  G11C2207/2245

摘要： A dynamic random access memory device includes a memory plane including at least one first matrix of memory cells, a read/write amplifier connected to the end of each column of the matrix, and at least one pair of input/output lines associated with the matrix. The dynamic random access memory device also includes at least one cache memory stage connected to each amplifier and is disposed in the immediate vicinity of this amplifier. The cache memory stage includes a static random access memory cell connected between the read/write amplifier and the pair of input/output lines.

摘要翻译： 动态随机存取存储器件包括存储器平面，该存储器平面包括至少一个存储单元的第一矩阵，连接到该矩阵的每列的末端的读/写放大器以及与矩阵相关联的至少一对输入/输出线 。 动态随机存取存储器还包括连接到每个放大器的至少一个高速缓存存储器级并且被布置在该放大器的紧邻附近。 高速缓冲存储器级包括连接在读/写放大器和输入/输出对之间的静态随机存取存储单元。

公开(公告)号：US06525958B2

公开(公告)日：2003-02-25

申请号：US10047184

申请日：2001-10-23

申请人： Scott J. Derner

发明人： Scott J. Derner

IPC分类号： G11C1156

CPC分类号： G11C5/066 ,  G11C11/56

摘要： A method and memory circuits for increasing the data bandwidth per microprocessor operation cycle is provided. The memory circuits provide the additional bandwidth without additional input/output (I/O) pins or requiring decreased cycle times. Multiple bits of data are passed through a single input/output pin with each operation cycle. The multiple bits of data are stored in or retrieved from multiple memory cells in each cycle. The I/O pins carry analog signals which represent multiple values of binary data This method of compressing data can be applied to any device that would benefit from the ability to transfer more data through a limited number of I/O pins.

摘要翻译： 提供了一种用于增加每个微处理器操作周期的数据带宽的方法和存储器电路。 存储器电路提供额外的带宽，无需额外的输入/输出（I / O）引脚或需要缩短周期时间。 每个操作周期，多位数据通过单个输入/输出引脚。 在每个周期中，多个数据位被存储在多个存储器单元中或从多个存储器单元中检索。 I / O引脚承载表示二进制数据的多个值的模拟信号。这种压缩数据的方法可以应用于受益于通过有限数量的I / O引脚传输更多数据的能力的任何器件。

公开(公告)号：US06418047B1

公开(公告)日：2002-07-09

申请号：US09757108

申请日：2001-01-08

申请人： Baher S. Haroun

发明人： Baher S. Haroun

IPC分类号： G11C1156

摘要： A system for storing data in read-only memory is disclosed that comprises bit level conductors, transistors, and sets of reference level conductors. Each reference level conductor has a reference value. A selected reference level conductor transmits a selected reference value to one of the transistors. The transistor transmits the selected reference value to a selected bit level conductor having a selected bit value. The bit level conductors, the transistors and the reference level conductors store data by encoding data as a combination comprising the selected bit value and the selected reference value. A method for storing data in read-only memory is disclosed. Bit level conductors having bit values, transistors, and sets of reference level conductors having reference values are provided. A selected bit value of a selected bit level conductor and a selected reference value of a selected reference level conductor are selected. Data is encoded by translating the data from a digital form to a combination comprising the selected bit value and the selected reference value. The data is stored by coupling the selected bit level conductor to the selected reference level conductor such that the selected reference level conductor can transmit the selected reference value to the selected bit level conductor.

公开(公告)号：US06301149B1

公开(公告)日：2001-10-09

申请号：US09513598

申请日：2000-02-25

申请人： Rino Micheloni ,  Giovanni Campardo

发明人： Rino Micheloni ,  Giovanni Campardo

IPC分类号： G11C1156

CPC分类号： G11C11/5642

摘要： The sensing circuits comparing the current flowing in the cell with a plurality of reference currents are not identical to each other but differently amplify the compared currents. In particular, the sensing circuit associated with the lowest reference current amplifies the cell current more than the other sensing circuits and to the respective reference current. The current dynamics is thereby increased and it is possible to keep the reading voltage low, since the inherent characteristic of the lowest reference current may be very close to or directly superimposed on that of the immediately preceding memory cell current distribution, retaining the possibility of discriminating between the different logic levels.

摘要翻译： 将在单元中流动的电流与多个参考电流进行比较的感测电路彼此不相同，但是不同地放大比较的电流。 特别地，与最低参考电流相关联的感测电路比其他感测电路和相应的参考电流更多地放大电池电流。 因此，由于最低参考电流的固有特性可能非常接近或直接叠加在紧邻的前一个存储单元电流分布的固有特性上，因此电流动态由此增加，并且可以保持读取电压低，从而保持识别的可能性 在不同的逻辑层次之间。

公开(公告)号：US06181596B2

公开(公告)日：2001-01-30

申请号：US09458766

申请日：1999-12-10

申请人： Stephen C. Horne ,  Michael R. Seningen ,  James S. Blomgren

发明人： Stephen C. Horne ,  Michael R. Seningen ,  James S. Blomgren

IPC分类号： G11C1156

CPC分类号： H03K19/0813 ,  G06F1/08 ,  G06F5/015 ,  G06F7/02 ,  G06F7/026 ,  G06F7/483 ,  G06F7/49 ,  G06F7/508 ,  G06F7/5443 ,  G06F17/5045 ,  G06F2207/3824 ,  G11C7/1006 ,  G11C8/00 ,  G11C8/10 ,  G11C8/16 ,  G11C8/18 ,  G11C11/418 ,  G11C11/419 ,  G11C11/56 ,  G11C19/00 ,  H03K19/0002 ,  H03K19/00346 ,  H03K19/00361 ,  H03K19/00384 ,  H03K19/0963 ,  H03K19/215

摘要： A memory device having a sense trigger coupled to receive an address when available, and to assert a sense trigger signal to the sense trigger when the sense trigger receives the address. The memory device also has an N-NARY, or 1-of-N, input logic gate that provides additional assurance that no more than one word line is asserted when an address is decoded. The memory device also has an N-NARY, or 1-of-N, output driver logic gate that provides an output signal directly useful for providing to another (N-NARY) 1-of-N logic gate.

摘要翻译： 具有感测触发器的存储器件，其在耦合到可用时接收地址，并且当感测触发器接收到地址时，将感测触发信号置于感测触发器。 存储器件还具有N-NARY或1-N输入逻辑门，其提供额外的保证，即当解码地址时不超过一个字线被断言。 存储器件还具有N-NARY或1-N输出驱动器逻辑门，其提供直接用于提供给另一（N-NARY）1-N逻辑门的输出信号。

公开(公告)号：US06721202B1

公开(公告)日：2004-04-13

申请号：US10027553

申请日：2001-12-21

申请人： Manoj B. Roge ,  Ajay Srikrishna

发明人： Manoj B. Roge ,  Ajay Srikrishna

IPC分类号： G11C1156

CPC分类号： G11C15/04

摘要： Architecture, circuitry and method are provided for a ternary content addressable memory (TCAM), and use thereof. Each TCAM cell is relatively small in size. If the TCAM cell is called upon to store voltage values indefinitely, provided power is retained on the cell, the TCAM cell employs no more than 16 transistors. Additional savings in size is achieved by using a single common conductor (or dual common conductors in a differential arrangement) to suffice as both the bit line and compare line. The common bit line and compare line connects to not only the X memory cell, but also the Y memory cell and the compare circuit of the TCAM cell. The compare circuit can either be activated or deactivated. During a compare operation, the compare circuit is selectively activated by placing a ground supply upon a match line enable conductor. The ground supply is imputed upon the match line whenever a mismatch occurs to designate that mismatch. Otherwise, during a normal read or write operation, the match line enable is placed at the same voltage value as the pre-charged match line.

摘要翻译： 提供三元内容可寻址存储器（TCAM）的架构，电路和方法及其使用。 每个TCAM单元的尺寸相对较小。 如果TCAM单元被无限期地存储电压值，则提供的功率保留在单元上，TCAM单元采用不超过16个晶体管。 通过使用单个公共导体（或差分布置中的双公共导体）来实现尺寸的额外节省，足以作为位线和比较线。 公共位线和比较线不仅连接X存储单元，还连接了TC存储单元和TCAM单元的比较电路。 比较电路可以被激活或禁用。 在比较操作期间，通过将接地电源放置在匹配线使能导体上来选择性地激活比较电路。 每当发生不匹配以指定不匹配时，地面电源就会在匹配线上进行估算。 否则，在正常读或写操作期间，匹配线使能被置于与预充电匹配线相同的电压值。

公开(公告)号：USRE38166E1

公开(公告)日：2003-07-01

申请号：US09410164

申请日：1999-09-30

申请人： Cristiano Calligaro ,  Vincenzo Daniele ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Nicola Telecco ,  Guido Torelli

发明人： Cristiano Calligaro ,  Vincenzo Daniele ,  Roberto Gastaldi ,  Alessandro Manstretta ,  Nicola Telecco ,  Guido Torelli

IPC分类号： G11C1156

CPC分类号： G11C11/5621 ,  G11C11/5642 ,  G11C2211/5632

摘要： A sensing circuit for serial dichotomic sensing of multiple-level memory cells which can take one programming level among a plurality of m=2n (n>=2) different programming levels, comprises biasing means for biasing a memory cell to be sensed in a predetermined condition, so that the memory cell sinks a cell current with a value belonging to a plurality of m distinct cell current values, each cell current value corresponding to one of the programming levels, a current comparator for comparing the cell current with a reference current generated by a variable reference current generator, and a successive approximation register supplied with an output signal of the current comparator and controlling the variable reference current generator. The variable reference current generator comprises an offset current generator permanently coupled to the current comparator, and m−2 distinct current generators, independently activatable by the successive approximation register, each one generating a current equal to a respective one of the plurality of cell current values.

摘要翻译： 用于在多个m = 2n（n> = 2）不同编程级别中可以采用一个编程级的多级存储器单元的串行二分感测的感测电路包括偏置装置，用于以预定的方式偏置待感测的存储器单元 条件，使得存储器单元以属于多个m个不同的单元电流值的值吸收单元电流，每个单元电流值对应于一个编程电平，用于将单元电流与产生的参考电流进行比较的电流比较器 通过可变参考电流发生器和逐次逼近寄存器来提供电流比较器的输出信号并控制可变参考电流发生器。 可变参考电流发生器包括永久地耦合到电流比较器的偏移电流发生器和由逐次逼近寄存器独立激活的m-2个不同的电流发生器，每个电流发生器产生等于多个电池电流值中的相应一个的电流 。