公开(公告)号：US10586865B2

公开(公告)日：2020-03-10

申请号：US15720977

申请日：2017-09-29

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Scott Warrick ,  Justin Dougherty ,  Alexander Barr ,  Christian Larsen ,  Marc L. Tarabbia ,  Ying Ying

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/786 ,  H01L29/06 ,  H01L21/761 ,  H01L21/762 ,  H01L29/423

Abstract: A dual-gate metal-oxide-semiconductor field-effect transistor (MOSFET) may include a MOSFET having a channel region, a drain, and a source, a first gate formed proximate to the channel region, a drain extension region formed proximate to the drain, and a second gate formed proximate to the drain extension region.

公开(公告)号：US09853103B2

公开(公告)日：2017-12-26

申请号：US15093574

申请日：2016-04-07

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Shanjen Pan ,  Marc L. Tarabbia ,  John L. Melanson

IPC: H01L29/84 ,  H01L29/10 ,  H01L29/808 ,  H01L29/66 ,  B81B3/00

CPC classification number: H01L29/1083 ,  B81B3/0027 ,  B81B2201/0257 ,  B81B2203/0127 ,  B81B2207/015 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/66901 ,  H01L29/808

Abstract: A JFET structure may be formed such that the channel region is isolated from the substrate to reduce parasitic capacitance. For example, instead of using a deep well as part of a gate structure for the JFET, the deep well may be used as an isolation region from the surrounding substrate. As a result, the channel in the JFET may be pinched laterally between doped regions located between the source and the drain of the JFET. In other example embodiments, the channel may be pinched vertically and the isolation between the JFET structure and the substrate is maintained. A JFET structure with improved isolation from the substrate may be employed in some embodiments as a low-noise amplifier. In particular, the low-noise amplifier may be coupled to small signal devices, such as microelectromechanical systems (MEMS)-based microphones.

公开(公告)号：US20230223274A1

公开(公告)日：2023-07-13

申请号：US18150398

申请日：2023-01-05

Applicant: CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD.

Inventor： Marc L. Tarabbia ,  Scott P. Warrick ,  Winston S. Blackley

IPC: H01L21/322 ,  H01L21/70 ,  H01L23/31 ,  H01L21/02 ,  H01L21/311 ,  H01L21/56 ,  H01L27/01 ,  H01L23/522

CPC classification number: H01L21/3221 ,  H01L21/707 ,  H01L23/3107 ,  H01L28/24 ,  H01L21/02172 ,  H01L21/02337 ,  H01L21/31144 ,  H01L21/56 ,  H01L27/016 ,  H01L23/5226

Abstract: An integrated circuit (IC) substrate manufacturing process provides time-dependent device characteristic variation due to hydrogen absorption by including one or more gettering layers near the devices that would otherwise absorb hydrogen and exhibit the variation as the hydrogen migrates in the devices. The method includes forming or mounting the devices on a top surface of the semiconductor wafer in die areas of the substrate, forming semiconductor structures in the semiconductor die areas, forming a getter layer above or adjacent to the devices in the die areas, and processing the wafer with one or more processes exposing the wafer to vapor having a hydrogen content, whereby an amount of hydrogen absorbed by the devices is reduced by presence of the getter layer. The method produces wafers including semiconductor dies with reduced hydrogen absorption by the devices and packaged ICs including the dies.

公开(公告)号：US20170272042A1

公开(公告)日：2017-09-21

申请号：US15072097

申请日：2016-03-16

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Shanjen Pan ,  Marc L. Tarabbia ,  Christian Larsen

IPC: H03F3/185 ,  H03F3/217 ,  H01L27/02 ,  H01L21/8234 ,  H01L29/08 ,  H01L27/088

CPC classification number: H03F3/185 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0207 ,  H01L27/088 ,  H01L28/00 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/66659 ,  H03F3/187 ,  H03F3/2171 ,  H03F3/2178 ,  H03F3/45475 ,  H03F2200/03 ,  H03F2200/366

Abstract: Transistors may be manufactured with a shared drain to reduce die area consumed by circuitry. In one example, two transistors can be manufactured that include two body regions that abut a shared drain region. The two transistors can be independently operated by coupling terminals to a source and a gate for each transistor and the shared drain. Characteristics of the two transistors can be controlled by adjusting feature sizes, such as overlap between the gate and the shared drain for a transistor. In particular, two transistors with different voltage requirements can be manufactured using a shared drain structure, which can be useful in amplifier circuitry and in particular Class-D amplifiers.

公开(公告)号：US20160322455A1

公开(公告)日：2016-11-03

申请号：US15094488

申请日：2016-04-08

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Scott Allan Woodford ,  John Christopher Tucker ,  Marc L. Tarabbia

IPC: H01L49/02 ,  H01L29/06 ,  H01L23/498 ,  H01L27/06

CPC classification number: H01L28/24 ,  H01L23/5228 ,  H01L27/0629 ,  H01L29/0657

Abstract: An integrated sense resistor within an integrated circuit (IC) may be surroundingly positioned near and coupled to a connection such as a pin or ball. The integrated sense resistor may be shaped such that more surface area of the integrated sense resistor is coupled to be positioned closer or in actual contact with the pin or ball than conventional straight layered integrated sense resistor solutions. The integrated sense resistor may be a non-straight shape that entirely surrounds or wraps around a connection to the pin or ball, such as a circular or oval shape, a box or rectangular shape, a triangular shape, or a polygonal shape. The integrated sense resistor may be a non-straight shape that partially surrounds a connection to the pin or ball, such as an open-circular or semi-circular shape, an open-sided box or rectangular shape, an open-sided triangular shape, an angular shape, or an open curved shape.

Abstract translation: 集成电路（IC）内的集成检测电阻器可以围绕定位在靠近并耦合到诸如针或球的连接。 集成检测电阻器可以被成形为使得集成检测电阻器的更多的表面积被耦合以比传统的直层分层集成检测电阻器解决方案更靠近或实际地接触销或球。 集成检测电阻器可以是非直线形状，其完全围绕或缠绕在与球或球的连接处，例如圆形或椭圆形，箱形或矩形形状，三角形形状或多边形形状。 集成检测电阻器可以是非直线形状，其部分地围绕与销或球的连接，例如开放圆形或半圆形形状，开放侧盒或矩形形状，开放三角形形状， 角形或开放弯曲形状。

公开(公告)号：US10123143B2

公开(公告)日：2018-11-06

申请号：US15276437

申请日：2016-09-26

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Vamsikrishna Parupalli ,  Lingli Zhang ,  Jeremy Babcock ,  Marc L. Tarabbia

IPC: H04R29/00 ,  H04R3/00

Abstract: Errors in measurements of a resistor to monitor current through a speaker may be corrected to improve the accuracy, performance, or quality of other signals affected by the measurement. Error may occur in the current measurement resulting from variations in measurements involving the resistor, such as errors based on the sense resistor's response to temperature or voltage differential. Correcting the measurement errors can prevent the overcurrent condition from occurring, and otherwise improve audio output from the speaker. Thus, a method for correcting measurements in a speaker monitoring circuit may include monitoring a current through a speaker by receiving a measurement that is correlated to the current output through the speaker; and correcting the measurement for one or more inaccuracies in the measurement.

公开(公告)号：US20180091911A1

公开(公告)日：2018-03-29

申请号：US15276437

申请日：2016-09-26

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Vamsikrishna Parupalli ,  Lingli Zhang ,  Jeremy Babcock ,  Marc L. Tarabbia

IPC: H04R29/00 ,  H04R3/00

CPC classification number: H04R29/001 ,  H04R3/007

Abstract: Errors in measurements of a resistor to monitor current through a speaker may be corrected to improve the accuracy, performance, or quality of other signals affected by the measurement. Error may occur in the current measurement resulting from variations in measurements involving the resistor, such as errors based on the sense resistor's response to temperature or voltage differential. Correcting the measurement errors can prevent the overcurrent condition from occurring, and otherwise improve audio output from the speaker. Thus, a method for correcting measurements in a speaker monitoring circuit may include monitoring a current through a speaker by receiving a measurement that is correlated to the current output through the speaker; and correcting the measurement for one or more inaccuracies in the measurement.

公开(公告)号：US09929147B2

公开(公告)日：2018-03-27

申请号：US15144657

申请日：2016-05-02

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Zhonghai Shi ,  Marc L. Tarabbia

IPC: H01L27/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L49/02 ,  H01L27/08

CPC classification number: H01L27/0629 ,  H01L21/823431 ,  H01L27/0805 ,  H01L28/86 ,  H01L28/90 ,  H01L29/66795 ,  H01L29/7851

Abstract: A vertical structure may be manufactured in a substrate of an integrated circuit, and that vertical structure used to form a high density capacitance for the integrated circuit. These thin vertical structures can be configured to operate as an insulator in a capacitor. The vertical structures may be manufactured using three-dimensional semiconductor manufacturing technology, such as FinFET (fin field effect transistor) technology and manufacturing processes. The capacitors based on thin vertical structures may be integrated with other circuitry that can utilize the thin vertical structures, such as FinFET transistors.

公开(公告)号：US20170294512A1

公开(公告)日：2017-10-12

申请号：US15093574

申请日：2016-04-07

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Shanjen Pan ,  Marc L. Tarabbia ,  John L. Melanson

IPC: H01L29/10 ,  H01L29/66 ,  B81B3/00 ,  H01L29/808

CPC classification number: H01L29/1083 ,  B81B3/0027 ,  B81B2201/0257 ,  B81B2203/0127 ,  B81B2207/015 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/66901 ,  H01L29/808

Abstract: A JFET structure may be formed such that the channel region is isolated from the substrate to reduce parasitic capacitance. For example, instead of using a deep well as part of a gate structure for the JFET, the deep well may be used as an isolation region from the surrounding substrate. As a result, the channel in the JFET may be pinched laterally between doped regions located between the source and the drain of the JFET. In other example embodiments, the channel may be pinched vertically and the isolation between the JFET structure and the substrate is maintained. A JFET structure with improved isolation from the substrate may be employed in some embodiments as a low-noise amplifier. In particular, the low-noise amplifier may be coupled to small signal devices, such as microelectromechanical systems (MEMS)-based microphones.

公开(公告)号：US20160329321A1

公开(公告)日：2016-11-10

申请号：US15144657

申请日：2016-05-02

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Zhonghai Shi ,  Marc L. Tarabbia

IPC: H01L27/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L49/02

CPC classification number: H01L27/0629 ,  H01L21/823431 ,  H01L27/0805 ,  H01L28/86 ,  H01L28/90 ,  H01L29/66795 ,  H01L29/7851

Abstract: A vertical structure may be manufactured in a substrate of an integrated circuit, and that vertical structure used to form a high density capacitance for the integrated circuit. These thin vertical structures can be configured to operate as an insulator in a capacitor. The vertical structures may be manufactured using three-dimensional semiconductor manufacturing technology, such as FinFET (fin field effect transistor) technology and manufacturing processes. The capacitors based on thin vertical structures may be integrated with other circuitry that can utilize the thin vertical structures, such as FinFET transistors.

Abstract translation: 可以在集成电路的基板中制造垂直结构，并且该垂直结构用于为集成电路形成高密度电容。 这些薄的垂直结构可以被配置为在电容器中作为绝缘体工作。 可以使用诸如FinFET（鳍场效应晶体管）技术和制造工艺的三维半导体制造技术来制造垂直结构。 基于薄垂直结构的电容器可以与可以利用诸如FinFET晶体管的薄垂直结构的其它电路集成。