公开(公告)号：US20070080390A1

公开(公告)日：2007-04-12

申请号：US11431265

申请日：2006-05-10

申请人： Christian Geissler ,  Franz Schuler ,  Danny Shum

发明人： Christian Geissler ,  Franz Schuler ,  Danny Shum

IPC分类号： H01L29/788

CPC分类号： G11C16/0416

摘要： An integrated memory transistor and a memory unit including a plurality of integrated memory transistors is disclosed. Generally, the integrated memory transistor includes an electron source, a channel region, a control region, a charge storage region, a source-side pocket doping region, and a drain-side pocket doping region. The electron source is operable to transport electrons to the channel region when the integrated memory transistor operates in a read mode. Further, the electron source includes a drain terminal region and a source terminal region. The channel region is arranged between the drain terminal region and source terminal region. The charge storage region is arranged between the control region and the channel region. The source-side doping region is arranged nearer to the source terminal region than to the drain terminal region. The drain-side pocket doping region is arranged asymmetrical to the source-side pocket doping region.

摘要翻译： 公开了一种集成存储晶体管和包括多个集成存储晶体管的存储单元。 通常，集成存储晶体管包括电子源，沟道区，控制区，电荷存储区，源极侧掺杂区和漏极侧杂质掺杂区。 当集成存储晶体管以读取模式工作时，电子源可操作以将电子传输到沟道区域。 此外，电子源包括漏极端子区域和源极端子区域。 沟道区域布置在漏极端子区域和源极端子区域之间。 电荷存储区域设置在控制区域和沟道区域之间。 源极侧掺杂区域比漏极端子区域更靠近源极端子区域。 漏极侧杂质掺杂区域与源极侧掺杂区域不对称地布置。

公开(公告)号：US07433232B2

公开(公告)日：2008-10-07

申请号：US11431265

申请日：2006-05-10

申请人： Christian Geissler ,  Franz Schuler ,  Danny Pak-Chum Shum

发明人： Christian Geissler ,  Franz Schuler ,  Danny Pak-Chum Shum

IPC分类号： G11C16/04

CPC分类号： G11C16/0416

摘要： An integrated memory transistor and a memory unit including a plurality of integrated memory transistors is disclosed. Generally, the integrated memory transistor includes an electron source, a channel region, a control region, a charge storage region, a source-side pocket doping region, and a drain-side pocket doping region. The electron source is operable to transport electrons to the channel region when the integrated memory transistor operates in a read mode. Further, the electron source includes a drain terminal region and a source terminal region. The channel region is arranged between the drain terminal region and source terminal region. The charge storage region is arranged between the control region and the channel region. The source-side doping region is arranged nearer to the source terminal region than to the drain terminal region. The drain-side pocket doping region is arranged asymmetrical to the source-side pocket doping region.

摘要翻译： 公开了一种集成存储晶体管和包括多个集成存储晶体管的存储单元。 通常，集成存储晶体管包括电子源，沟道区，控制区，电荷存储区，源极侧掺杂区和漏极侧杂质掺杂区。 当集成存储晶体管以读取模式工作时，电子源可操作以将电子传输到沟道区域。 此外，电子源包括漏极端子区域和源极端子区域。 沟道区域设置在漏极端子区域和源极端子区域之间。 电荷存储区域设置在控制区域和沟道区域之间。 源极侧掺杂区域比漏极端子区域更靠近源极端子区域。 漏极侧杂质掺杂区域与源极侧掺杂区域不对称地布置。

公开(公告)号：US20180092443A1

公开(公告)日：2018-04-05

申请号：US15282633

申请日：2016-09-30

申请人： Sven Albers ,  Klaus Reingruber ,  Andreas Wolter ,  Georg Seidemann ,  Christian Geissler ,  Thorsten Meyer ,  Gerald Ofner

发明人： Sven Albers ,  Klaus Reingruber ,  Andreas Wolter ,  Georg Seidemann ,  Christian Geissler ,  Thorsten Meyer ,  Gerald Ofner

IPC分类号： A44C5/02 ,  H04B1/3827 ,  A45F5/00 ,  A44C5/00 ,  G01D11/30 ,  A61B5/0205 ,  A61B5/00

CPC分类号： G06F1/163 ,  A44C5/00 ,  A44C5/02 ,  A44C5/105 ,  A45F5/00 ,  A45F2005/008 ,  A45F2200/0508 ,  A61B5/02055 ,  A61B5/021 ,  A61B5/02438 ,  A61B5/1112 ,  A61B5/681 ,  A61B2560/0257 ,  A61B2560/0443 ,  A61B2562/0219 ,  G04B37/1486 ,  G04B47/00 ,  H04B1/385

摘要： A flexible band wearable electronic device includes a plurality of rigid links. The flexible band wearable electronic device also includes a number of pivot joints coupling the plurality of rigid links together. The flexible band wearable electronic device further includes a first electronic device on a first of the plurality of rigid links, and a second electronic device on a second of the plurality of rigid links. The flexible band wearable electronic device still further includes an electrical communication pathway between first electronic device and the second electronic device and through at least a portion of one of the number of pivot joints.

公开(公告)号：US09252251B2

公开(公告)日：2016-02-02

申请号：US13330205

申请日：2011-12-19

申请人： Franz Hirler ,  Ralf Siemieniec ,  Christian Geissler ,  Oliver Blank ,  Maximilian Roesch

发明人： Franz Hirler ,  Ralf Siemieniec ,  Christian Geissler ,  Oliver Blank ,  Maximilian Roesch

IPC分类号： H01L29/739 ,  H01L29/66 ,  H01L29/78 ,  H01L29/861 ,  H01L29/872 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423

CPC分类号： H01L29/7397 ,  H01L29/0615 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/42376 ,  H01L29/66674 ,  H01L29/66734 ,  H01L29/7801 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/872

摘要： A semiconductor component is disclosed. One embodiment includes a semiconductor body including a first semiconductor layer having at least one active component zone, a cell array with a plurality of trenches, and at least one cell array edge zone. The cell array edge zone is only arranged in an edge region of the cell array, adjoining at least one trench of the cell array, and being at least partially arranged below the at least one trench in the cell array.

摘要翻译： 公开了半导体部件。 一个实施例包括半导体本体，其包括具有至少一个有源分量区的第一半导体层，具有多个沟槽的单元阵列和至少一个单元阵列边缘区。 单元阵列边缘区域仅布置在单元阵列的边缘区域中，邻接单元阵列的至少一个沟槽，并且至少部分地布置在单元阵列中的至少一个沟槽的下方。

公开(公告)号：US20150266728A1

公开(公告)日：2015-09-24

申请号：US14731211

申请日：2015-06-04

申请人： Christian Geissler ,  Thorsten Meyer ,  Gerald Ofner ,  Reinhard Mahnkopf ,  Andreas Augustin ,  Christian Mueller

发明人： Christian Geissler ,  Thorsten Meyer ,  Gerald Ofner ,  Reinhard Mahnkopf ,  Andreas Augustin ,  Christian Mueller

IPC分类号： B81C1/00

CPC分类号： B81C1/00666 ,  B81B7/0054 ,  B81C1/00261 ,  B81C1/00349 ,  B81C2203/0136 ,  B81C2203/0154 ,  H01L21/568 ,  H01L23/3135 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/24137 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/73207 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73277 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： Stress buffer layers for integrated microelectromechanical systems (MEMS) are described. For example, a semiconductor package includes a substrate having first and second surfaces, the second surface having an array of external conductive contacts. A microelectromechanical system (MEMS) component is disposed above the first surface of the substrate. A buffer layer is disposed above the MEMS component, the buffer layer having a first Young's modulus. A mold compound is disposed above the buffer layer, the mold compound having a second Young's modulus higher than the first Young's modulus.

摘要翻译： 描述了用于集成微机电系统（MEMS）的应力缓冲层。 例如，半导体封装包括具有第一和第二表面的衬底，第二表面具有外部导电触点阵列。 微机电系统（MEMS）部件设置在基板的第一表面上方。 缓冲层设置在MEMS部件上方，缓冲层具有第一杨氏模量。 模具化合物设置在缓冲层上方，模塑料具有高于第一杨氏模量的第二杨氏模量。

公开(公告)号：US08786105B1

公开(公告)日：2014-07-22

申请号：US13739045

申请日：2013-01-11

申请人： Thorsten Meyer ,  Sven Albers ,  Christian Geissler ,  Andreas Wolter ,  Markus Brunnbauer ,  David O'Sullivan ,  Frank Zudock ,  Jan Proschwitz

发明人： Thorsten Meyer ,  Sven Albers ,  Christian Geissler ,  Andreas Wolter ,  Markus Brunnbauer ,  David O'Sullivan ,  Frank Zudock ,  Jan Proschwitz

IPC分类号： H01L23/48 ,  H01L21/00

CPC分类号： H01L23/315 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/562 ,  H01L24/19 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

摘要： A semiconductor device is described having at least one semiconductor chip, the chip having an active area on a top side thereof, the active area formed at least in part of low-k material, said low-k material defining a low-k subarea of said active area; an embedding material, in which said at least one semiconductor chip is embedded, at least part of the embedding material forming a coplanar area with said active area; at least one contact area within the low-k subarea; a redistribution layer on the coplanar area, the redistribution layer connected to said contact areas; at least one first-level interconnect, located outside said low-k subarea, the first-level interconnect electrically connected to at least one of said contact areas via the redistribution layer.

摘要翻译： 描述了半导体器件，其具有至少一个半导体芯片，该芯片在其顶侧具有有源区，至少部分形成在低k材料上的有源区，所述低k材料限定低k分区 说活跃区; 嵌入材料，其中所述至少一个半导体芯片被嵌入，所述嵌入材料的至少一部分与所述有源区域形成共面区域; 低k子区域内的至少一个接触区域; 在共面区域上的再分配层，再分配层连接到所述接触区域; 位于所述低k子区域外的至少一个第一级互连，所述第一级互连经由再分配层电连接到所述接触区域中的至少一个。

公开(公告)号：US20150243572A1

公开(公告)日：2015-08-27

申请号：US14189938

申请日：2014-02-25

申请人： Sven Albers ,  Sonja Koller ,  Thorsten Meyer ,  Georg Seidemann ,  Christian Geissler ,  Andreas Wolter

发明人： Sven Albers ,  Sonja Koller ,  Thorsten Meyer ,  Georg Seidemann ,  Christian Geissler ,  Andreas Wolter

IPC分类号： H01L23/31 ,  H01L21/56

CPC分类号： H01L21/56 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2924/00

摘要： Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a die having a first side and a second side disposed opposite to the first side. The IC package may further include an encapsulation material encapsulating at least a portion of the die and having a first surface that is adjacent to the first side of the die and a second surface disposed opposite to the first surface. In embodiments, the second surface may be shaped such that one or more cross-section areas of the IC package are thinner than one or more other cross-section areas of the IC package. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例涉及集成电路（IC）封装，其包括具有与第一侧相对设置的第一侧和第二侧的管芯。 IC封装还可以包括封装模具的至少一部分并且具有与模具的第一侧相邻的第一表面的封装材料和与第一表面相对设置的第二表面。 在实施例中，第二表面可以被成形为使得IC封装的一个或多个横截面积比IC封装的一个或多个其它横截面积更薄。 可以描述和/或要求保护其他实施例。

公开(公告)号：US08598709B2

公开(公告)日：2013-12-03

申请号：US12871939

申请日：2010-08-31

申请人： Thorsten Meyer ,  Gottfried Beer ,  Christian Geissler ,  Thomas Ort ,  Klaus Pressel ,  Bernd Waidhas ,  Andreas Wolter

发明人： Thorsten Meyer ,  Gottfried Beer ,  Christian Geissler ,  Thomas Ort ,  Klaus Pressel ,  Bernd Waidhas ,  Andreas Wolter

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/5389 ,  H01L21/568 ,  H01L24/05 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L25/0655 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05547 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/18162 ,  H01L2924/00

摘要： A method and a system for routing electrical connections are disclosed. A semiconductor device includes a first semiconductor chip and a routing plane having a plurality of routing lines. A first connecting line is electrically coupled to the first semiconductor chip and one of the plurality of routing lines and a second connecting line is electrically coupled to the one of the plurality of routing lines and to one of a second semiconductor chip or a first external contact element.

摘要翻译： 公开了用于路由电连接的方法和系统。 半导体器件包括第一半导体芯片和具有多个布线线路的布线平面。 第一连接线电耦合到第一半导体芯片，并且多个布线线之一和第二连接线电耦合到多个路由线中的一个并且耦合到第二半导体芯片或第一外部触点之一 元件。

公开(公告)号：US20120153386A1

公开(公告)日：2012-06-21

申请号：US13330205

申请日：2011-12-19

申请人： Franz Hirler ,  Ralf Siemieniec ,  Christian Geissler ,  Oliver Blank ,  Maximilian Roesch

发明人： Franz Hirler ,  Ralf Siemieniec ,  Christian Geissler ,  Oliver Blank ,  Maximilian Roesch

IPC分类号： H01L27/088

CPC分类号： H01L29/7397 ,  H01L29/0615 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/42376 ,  H01L29/66674 ,  H01L29/66734 ,  H01L29/7801 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/872

摘要： A semiconductor component is disclosed. One embodiment includes a semiconductor body including a first semiconductor layer having at least one active component zone, a cell array with a plurality of trenches, and at least one cell array edge zone. The cell array edge zone is only arranged in an edge region of the cell array, adjoining at least one trench of the cell array, and being at least partially arranged below the at least one trench in the cell array.

摘要翻译： 公开了半导体部件。 一个实施例包括半导体本体，其包括具有至少一个有源分量区的第一半导体层，具有多个沟槽的单元阵列和至少一个单元阵列边缘区。 单元阵列边缘区域仅布置在单元阵列的边缘区域中，邻接单元阵列的至少一个沟槽，并且至少部分地布置在单元阵列中的至少一个沟槽的下方。

公开(公告)号：US20180095426A1

公开(公告)日：2018-04-05

申请号：US15282615

申请日：2016-09-30

申请人： Sven Albers ,  Klaus Reingruber ,  Andreas Wolter ,  Georg Seidemann ,  Christian Geissler ,  Thorsten Meyer ,  Gerald Ofner

发明人： Sven Albers ,  Klaus Reingruber ,  Andreas Wolter ,  Georg Seidemann ,  Christian Geissler ,  Thorsten Meyer ,  Gerald Ofner

IPC分类号： G04B37/14 ,  H04B1/3827 ,  A44C5/02 ,  A44C5/00 ,  A44C5/14

CPC分类号： G04B37/1486 ,  A44C5/0053 ,  A44C5/02 ,  A44C5/105 ,  A44C5/14 ,  G06F1/163 ,  H04B1/385 ,  H04B2001/3861 ,  H04W4/80

摘要： A flexible band wearable electronic device includes a plurality of rigid links. The flexible band wearable electronic device also includes a number of pivot joints coupling the plurality of rigid links together. The flexible band wearable electronic device further includes a first electronic device on a first of the plurality of rigid links, and a second electronic device on a second of the plurality of rigid links. The flexible band wearable electronic device still further includes an electrical communication pathway between first electronic device and the second electronic device and through at least a portion of one of the number of pivot joints.